JPS59216368A - Picture processing device - Google Patents

Abstract

PURPOSE:To make high-speed data processing and transmission by compressing and encoding picture data to store it in a storage device and performing processings of storing and reading transmission operations for every page of an original. CONSTITUTION:The picture signal inputted in serial from an original 10 by an image sensor 12 is converted to a binary signal by an A/D converter 14 and is inputted to a data compressing circuit 20. An MH code 25 and data 24 informing the code length of the MH code are outputted to a packing circuit 23 by a run length counter 21 and an MH encoder 22, and a joining processing of the code 25 is performed to form data having a prescribed effective code length, and these data are outputted successively. This output signal is stored in a buffer memory 15. An address controller 100 controls the storage into the memory and stores address data in an RAM 102 when one-page components of original are stored completely, and this data is read out from the memory as the start address of the second page to transmit stored data of the first page successively during the storage operation of the second page.

Description

TECHNICAL FIELD The present invention relates to a data compression device applicable to electronic files, etc., and to a data compression device that performs compression processing on input data according to a predetermined logic to form compressed data. It is.

BACKGROUND ART Conventionally, a technique is known in which highly redundant binary data such as a digital image signal read from an object is compressed according to a predetermined logic. For example, in so-called facsimile machines that transmit images using telephone lines5, compression technology is introduced to reduce the amount of data to be transmitted and to shorten the transmission time.

In addition, in recent years, electronic image file devices using laser disks and magnetic disks that can store large amounts of image data have been proposed, but if compression technology is introduced, the storage capacity of these storage media can be substantially increased. This is an effective way to encourage people to act.

By the way, the Modified Huffman method (M-H method) is well known as a data compression method.This method generally uses the so-called run length length, which is the number of consecutive white or black data in the original digital image data. is measured, and the image data is converted into a modified Hoffman code (MH code) according to the result.

The code length of this M@H code is not constant (
, the bit length varies from 2 bits to 13 bits corresponding to the run length.

Therefore, it is not easy to connect the MH codes and back them in byte or word units.

Conventionally, the above-mentioned facsimile machine does not require a very high scanning speed for reading Mj TAi images (also, by utilizing the fact that the mechanical operation for document scanning can be performed intermittently, The process of joining H codes was performed at low speed using a microcomputer or the like.

In recent years, high-speed data processing and transmission of electronic files and the like has become desired, and as a result, it has become necessary to process M and H data at high speed and in real time. However, conventional processing methods cannot completely meet this demand, and this is an impediment to speeding up the processing.

Purpose The present invention has been made in view of the above points, and an object thereof is to provide a data compression device that can fully meet the demands for high-speed data processing and transmission of electronic files, etc. It is.

Example Hereinafter, the present invention will be explained in more detail using the drawings.

FIG. 1 shows the configuration of an embodiment in which the present invention is applied to a document image reading device in an electronic filing device. The original 10 is illuminated by an illumination device (not shown), and the original 1o
The reflected light is focused by a lens 11 onto an image sensor 12 consisting of a CCD. A 12-image sensor with multiple photoelectric conversion elements arranged in the width direction of the document.
Serially outputs electrical signals according to the amount of input light. After the output of the image sensor 12 is amplified by the amplifier 16,
The /D converter 14 converts the image data into binary image data indicating white and black levels. 2 from A/D converter 14
The digitization code is input to the data compression circuit 2o. In the data compression circuit 2o, a run length counter 21 counts the number of consecutive white or black signals in the input binary signal. The M, H encoder 22 which receives this count value and a signal indicating the monochrome state outputs the M, H code 25 and data 24 indicating the code length of the M, H code to the puffing circuit 26 according to a well-known conversion table. . The backing circuit 23 uses the code length data 24 to perform a process of splicing the input M and H codes 25 whose code lengths are inconsistent.
Data of a predetermined effective code length (for example, 8 bits) is formed and sequentially output. Data sequentially output from the data compression circuit 20 is output as a serial signal in the buffer memory 15. This output signal is stored in a file device such as an optical disk, or transmitted to a remote receiving unit via a telephone line. Therefore, a high-speed file of data is possible on a small-capacity disk.

FIG. 2 is a circuit diagram showing a detailed configuration example of the data compression circuit 20 shown in FIG. This circuit example converts serial original image data into modified Huffman (M, H) codes as described above, and then backs these converted M and H code data with different bit lengths (code lengths). The data is converted into parallel data of a predetermined effective length, that is, 1 byte width, and outputted to an electronic file or the like.

Serial original image data VIDE obtained by scanning the manuscript
OId Rol, (run length) is input to the counter 21, and the run length lengths of white and black are determined.

At the same time, it is determined whether the input signal is of white level or black level. The determined gin length data R, L and the signal TS indicating the white and black states are stored in M and 11 (Modified Huffman) code conversion table is stored in R.
, 0M memories are input to the address lines of the M, H encoder 22. M, H encoder 22) J:,
ffjt Large 16-bit M. It converts into II code and generates a 4-bit signal indicating its effective code length.

(For example, if the M. ■■ code is 0011, the output of the M, H code conversion table is 0011 as the M, H code MC.
xxXxxxxxxxx (x is arbitrary), and the code length LC' is 4' (0100). ) M generated above. (2) The code MC and effective code length LC are input to the backing circuit 26 and are first stored in a FIFO (first-in/first-out buffer memory) 61.

In addition, the above-mentioned 11. A series of operations of the L counter 21, M-, H encoder 22, and FIFO 31 are performed in real time, for example, simultaneously with a constant speed reading operation in accordance with the transfer rate (clock φ) of the original image data VIDIX).

M, H code MC and effective code length 1 from FIFO31. C is read out and the MH codes are connected, ie, bit handling is performed. Here, FIF
The operation speed of reading from O31 and pit handling is more than twice the transfer speed of the original image data, taking into consideration data expansion due to ■\4I-1 conversion, and in this embodiment is 2φ, which is twice the transfer speed of the original image data. Also, if the speed is set too high, processing down time will occur for data supply, so it is not necessary to do so.

The M and H codes MC taken out from the FIFO 31 are sequentially moved from the register B52 to the register (13).
Finally, it is backed up into 8 pits, ie, 1 byte.

However, since the M and H codes MC have different code lengths depending on their run lengths, it is necessary to perform bit splicing processing on them. This is done using two 1/8 multiplexers, multiplexer P34 and multiplexer Q35. In addition, in the figure, the X mark of multiplexer P24 indicates an unused state.

The multiplexer Q35 serves to pack the subsequent M, H code MC stored in the register B62 into the lower order of the M, H code MC already stored in the register C33.

Also, the number of bits taken into multiplexer P34u register B32 and register C33 is
It plays the role of shifting the bits in the upper direction.

The effective code length is taken into count register X36 via multiplexer 4o. Furthermore, the addition circuit 67
The accumulated debt is added by the count register Y38. Based on the result of this addition, it is determined how many bits of data are finally stored in the register C53.

Multiplexer Q65 is instructed by signal SLC indicating the contents of count register Y3B to take in the data bits of register B32 from the lower bits of register C33.

Note that the finite number of bits in register C33H (8 in this circuit example)
Therefore, if all the data bits stored in the register B32 cannot be taken into the register C66, an overpuff '6-' occurs. in this case,
The remaining data bits not captured in register C66 will remain in register B'52. At this time,
This remaining number of bits is calculated by a subtraction circuit 39 which receives the value of the count register X66 and the value of the subtraction circuit 41 as input.
It is reset in the count register X56 through the multiplexer 40 which is selectively operated by the overflow signal OF from the adder circuit 37. As a result, a new PIF
The state is the same as when 1 bit of data is set from O31 to register B32.

Also, the remaining data bits of register B32 are stored in register C3.
It is necessary to fill in the upper part of the register B'52 by the amount of bits taken into the register B'52. Therefore, how many bits of data have been taken into register 033 is calculated by calculation circuit 41 which receives the number of effective bits (8 bits) and the value of count register Y, 158 as input. Then, this subtraction result is input as the selection signal 8LB to the multiplexer P34, and the register B32 is shifted in the upper direction.

Multiplexer P541-! It does not operate except when register C35 overflows. Therefore, register C
Code data qFIFO3 while there is no overflow of 33
1→register B32→(shift by multiplexer Q55)→register C33.

By the way, when register C33 overflows, FIFO
The code data reading operation from 31 is stopped. However, the stitching operation continues. That is, in parallel with the operation of filling the remaining bits of register B32 upward using multiplexer P34, a part of the bits of register B32 are packed into the lower part of register C33. (In this case) 1 byte of data is completely backed up to the register C33. ) Also, a signal of the buffer Mura Sora a may be output from the FIFO 31. At this time, the bit splicing process has caught up with the supply of image data, and the bit splicing operation is temporarily stopped.

FIG. 3(a) shows multiplexer P34 and register B32.
, FIG. 3(b) shows multiplexer Q35 and register C3.
3 shows the input/output relationship. Also, FIG. 4 shows the operation time chart of PIFO31, register B32, and register C33. −
) is shown.

In this way, for the code data taken into the FIFO 31, the data filling operation to the register C33 and the data taking including the shift operation in the register B32 are performed sequentially (the shift operation is performed in the register B32).
(If there is no residual data in filter 2, the order will not be processed.)・Also, by making the packing operation and shift operation twice as fast as 2φ compared to the storage speed φ of code data to the FIFO 61, high-speed real-time processing that also takes into account the data expansion of M and H conversion can be achieved. becomes possible.

As explained above, the M and H codes with uneven code lengths output from the M and H encoder 22 are input to the FIFO 31, and in the subsequent data processing, the MH codes are treated as parallel data and the bit splicing processing time is Shortening can be achieved. Therefore, the compression process for the input read signal is executed in real time without limiting the image reading operation according to the processing speed.

In this embodiment, the M and H code data are processed in units of 1 byte, but the process is not limited to this, and may be processed in units of 1 word depending on the processing device such as the subsequent electronic file or the data transfer standard. It can also be in units of several bytes. Further, in this case, it is natural to use a multiplexer suitable for the amount of backing, but the bit stuffing process by multiplexer Q35 and the shifting operation by multiplexer P34 can be achieved with the same configuration.

Further, the data processing speed may be twice or more the data supply speed.

In addition to the data to be subjected to backing processing, in addition to image read data converted into MH code, data compressed using other compression logic, and data read from semi-dedicated memory, magnetic memory, etc., converted according to a predetermined logic. Needless to say, the present invention can be applied to the tracking process of data of irregular data lengths output from various data output devices.

The memory 15 shown in FIG. 1 will be described in detail. This is effective when transmitting data using a communication line in a memory that stores encoded data. This has a capacity of 32 Mbytes, and since the data for one original is about 2 Mbytes, it can store data for about 16 originals. However, if the manuscript information is complicated, such as packed with characters, even if it is compressed, it will not work.
There may be cases where the data string can only be stored in about 6 sheets.

Moreover, if it is a single width and one document, it may be possible to store 20 or more sheets. Therefore, if the storage area for each document is set in advance in the memory, it is extremely uneconomical.

The present invention eliminates this drawback and enables effective use of memory.

In FIG. 1, 100 is a memory address control circuit for writing and reading data into and from the memory 15, and its address data is stored in I(, AM1Q2).

There are various kinds of address data as described below, and the CPU10
4 performs storage control and setting control via 110101. CGROM 106 is a memory for generating characters by software, and is used to synthesize date and time data into image data.
It is input to the 几 counter. In other words, characters are also encoded and synthesized.

Reference numeral 104 performs the above processing and has a clock function for displaying the date and time. To briefly explain, the 1-address controller 2100 controls the storage of the document in the memory, and when the storage of one page of the document is completed, the address data at that time is stored in AM102 as a stop address.Next, the second page of document is stored. Therefore, the address data is set in the controller 100 as the write start address.

When the second page of compressed data arrives, storage starts from its start address. On the other hand, the data stored in the first page is outputted from the memory for sequential transmission during the storage operation of the second page. It is prohibited to store new data on the first page unless the transmission of the first page is completed. After the second page, the sixth page is stored in the same manner. If 6
If the memory becomes full in the middle of the page, the storage continues by returning to the first page area only if the transmission of the first page has been completed.

The details will be explained below. Table 1 shows the control signals between the screen memory and the CPU taken into consideration in the above precautions.

Table 1 If the top address of the writable area is ■ and the end address is , then in the initial state of Figure 4, the write start address is ■, the memory end address is , the turnaround address is ■, and the inhibit area is The top is , and the read start address is ■.

FIG. 6 shows how images are stored in the empty memory.

(1) Specify the write start address ■ of the memory end address to the memory board and start reading the image. When reading of the first page ■ is completed and all data is converted to MH, 1 (, TC data is written and accumulation stops. The CPU senses that ILTC has been written and changes the memory address (current Address) ■ is memorized. Inhibit area top is set to ■.

(2) Set ■ to the start address of the next page and start reading the image. Loading is completed and page O
Once accumulated, the CPU senses and stores the stop address ◎.

(6) Set ◎+1 as the address of the next page and start reading page ■. When the distance to the inhibit address ■ reaches 5QQ K bits, an alarm will be generated from the memory board. In this case, since it is accumulation mode, CP
No communication measures such as UdCWC interruption will be taken. When the current address reaches the memory end address, the memory board advances the current address to the turnaround address ■. However, since the inhibit address is also ■, actual writing to the memory is prohibited from ■. It simply advances the current address. When the reading of the page (■) is completed, the CPU intelligently stores the stop address (■).

At this time, the CPU page is fixed at the start address O (no new stop address is set, and page 2 is effectively cleared).

This means that the CPU was able to know the amount of information on the page ■ from the stop address ◎. When the sending (or test copy) operation begins and the page becomes empty, click the page again.
Start reading.

(4) Finally, the accumulation ends at the write start address ◎, the memory end address, the turnaround address, the inhibit area top ■, and the read start address ■.

Figure 5 shows the case of sending in the mode where the original can be changed manually.

(5) When the storage was completed in the state of (4), the send button was pressed. The read start address is set to ■. Following page ■ and page ■, page ■ has address 0.
I remember which CPU is scheduled to be installed.

(6) Page ■The page whose memory is read from the beginning■
When all of the data have been transmitted, page (2) is written to the memory. The reading start address is set to [phase]. The top of the inhibit area moves to ■.

(7) Page ■ is read out (and at the same time page ■ is written. Page ■ finishes writing at address ◎. When page ■ has been sent, read the sister address and inhibit area top transitions to ◎. When the accumulation of page O is completed, page ■ is transmitted.

(8) When the transmission of page (■) is completed, the communication is terminated, the read start address and the vl write start address are returned to (■), and the inhibit area is top.

In other words, it does not return to the initial state.

In this way, the data is sent after storing multiple pages in the memory in advance, rather than every time one page is stored, so even if there is blank time required to manually replace the original, the communication line is not wasted. It becomes economical.

Figure 6 shows that when a transmission interruption request is made when the original is manually changed and sent, page (9) and page ■ are stored in the memory as M (14). However, the CPU knows that it will end with 0 when written.

(10) Start transmitting page G), and start transmitting page ■ while accumulating L page ■ to be transmitted.

Move the inhibit area top to ■.

(11) A CWC signal arrived from the receiving side during the transmission of page ■. When issuing an interrupt command to the CPU memory, R and TC are automatically inserted), and page 0 stops at address [phase]. The accumulation of page ■ has finished during this time. When receiving C 几C and starting to send images again, print out the rest of the page from the address ■ and end the communication after sending the page ■ In this way, you can use memory effectively and also When automatically exchanging the originals, there is almost no time for exchanging them, so by using the storage and transmission mode shown in Figure M3, multiple originals can be sent in a short time from the start of original reading. Further, in the case of manual replacement, the replacement time is long, so the modes shown in FIGS. 5 and 6 can save transmission interruption time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment in which the present invention is applied to a document reading device, FIG. 2 is a circuit diagram showing a detailed configuration example of the data compression circuit 20 shown in FIG. ) and (b)
gJλ4 is a time chart showing the operation timing of the circuit shown in the second diagram, and FIGS. 5 to 8 are memory explanatory diagrams.
encoder, 23 is a backing circuit, 31 is FIFo,
32 is a register B163 is a register C1-4 is a multiplexer P, 65 is a multiplexer Q136 is a count register X167 is an addition circuit, 38 is a count register Y
, 39.41 is a subtraction circuit, and 40 is a multiplexer. (61) (b) Figure 4: REerC visit
（／／）
1 Procedural amendment (method) % formula % Display of the case 1982 Patent application No. 90897 Name of the invention Image processing device Amendment person Relationship to the case Patent applicant Location 3-30-2 Shimomaruko, Ota-ku, Tokyo IW 146 Canon Co., Ltd., 3-30-2 Shimomaruko, Oide-ku, Tokyo (telephone: 75
8-2111) 5. Date of amendment order: August 60, 1982 (shipping date) 6. Application, specification and drawings subject to amendment 7. Contents of amendment

Claims (1)

[Claims] An image processing apparatus comprising means for encoding image data of a document, a memory for storing the encoded data, and a means for storing data corresponding to the amount of data stored in the memory for each document.