JPS59216226A - Data bus control system - Google Patents

Abstract

PURPOSE:To reduce the processing overhead of a microprocessor to improve the processing efficiency by providing a bus use request suppressing logic circuit, which is controlled by a bus use inhibiting flag, in each logic unit. CONSTITUTION:When a data bus use request signal comes from a micro-processor 12, it is judged whether a bus busy FF 14 is set or not, and resetting is waited if the FF 14 is set; but if it is reset, it is judged whether a bus error signal 18 exists or not. If the signal 18 exists, it is judged whether a bus use inhibiting flag 13 is ''1'' or not; and if it is ''1'', the bus use inhibiting processing to operate a suppressing logic circuit 15 is executed. Thus, the circuit 15 controlled by the flag 13 is provided in each logic unit to suppress the bus use request which is outputted to a bus control unit from a logic circuit unit requesting the bus use. Consequently, the processing overhead of the microprocessor is reduced to improve the processing efficiency.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data bus control method for a data processing device having a data bus that connects a plurality of logic circuits. [Background of the Invention] Conventionally, this type of data bus As shown in the flowchart of FIG. 1, the control method is such that the microprocessor that controls the data bus of the logical unit that makes the data bus use request checks whether the bus use prohibition flag is 1" or not in step 31. ), if it is 1'', bus use prohibition processing is performed (step 32), and if it is O'', a data bus request is issued (step 33).If a data bus request is issued, bus busy is set. Step 34)
If it remains set, wait until it is reset, and when it is reset, determine whether there is a bus error (step 35). If there is a bus error, perform path error processing (step 36); if there is no bus error, perform path error processing (step 36). Normal processing was being performed (step 37).

As mentioned above, in the conventional data bus control method, the microprocessor that controls the data bus issues a request to use the bus (after checking the bus use prohibition flag). The use prohibition flag is set when the bus is @minato or due to the status in the other party unit of data transfer, and the probability that the bus use prohibition flag is 1'' is small.

Therefore, in the conventional bus control method described above, although the nox use prohibition flag is generally 0'', it is necessary to confirm that the flag is 0'' before requesting the use of the bus.
As shown in FIG. 1, there is a drawback in that system control involves overhead and reduces the processing efficiency of the microprocessor. , [Object of the Invention] The present invention has been made in view of the above-mentioned points. In normal times when there is no congestion such as data transfer within the data processing device, that is, when the bus use prohibition flag is "0", It is an object of the present invention to provide a data bus control method that reduces the processing overhead of a microprocessor in a logical unit and improves the processing efficiency of the microprocessor.

[Summary of the invention]

The key point of the present invention is to suppress the bus use request signal output from the microprocessor in the logic unit by outputting a bus use prohibition flag and send it to the bus control unit, so that the microprocessor There is no need to check the bus use prohibition flag, and the bus control process is automatic.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram showing the configuration of a data processing device that uses a data bus. In the figure, 1-1 to 1-n are logic circuit units, and 2 is the logic circuit unit 1-1 to 1.
3 is a data bus transfer unit commonly connected to the data bus -n.

A plurality of control signal lines 4-1 to 4-n are provided between one logic circuit unit and data bus control unit 3.

FIG. 3 is a block diagram showing the configuration of the logic circuit unit. In the figure, 11 indicates one logic circuit unit, which includes a bus use request signal 16 and a bus use end signal 17.
, a bus error signal 18, and a bus stop instruction signal 4 are connected to the bus control unit 3. 1
2 is a microprocessor that performs bus control, and 13 is a bus use prohibition flag.

When bus congestion is detected, the data bus control unit 3 sets the bus use prohibition flag 13 according to the bus box use prohibition instruction (No. 8 22).
0'', if the microprocessor 2 makes a bus use request, the bus use instruction signal is sent to the inhibit logic circuit 1.
5, set the Bus Busy Clinon Nororan 14 and output the Bus Usage Value Request No. 6 10.

When the bus usage end signal 17 is sent to the logic circuit unit 11, the bus logic logic 14 is reset, but the microprocessor 12 sends this to the signal line 16.
Note that if any bus control error occurs, a bus error signal 18 is sent together with the bus use end signal 17, so that the bus error flip-flop 21 is set. The microprocessor 12 checks the noise error detection signal output from the bus error flip-flop 21, and also checks the noise delimitation signal. In this case, if the bus use prohibition signal 19 is 0"' and the bus use prohibition flag 13 is 61", even if the microprocessor issues the bus use request instruction signal z3, the inhibition logic circuit 15 )(busy flip-flop 14 is not set (So, in this case, the bus error flip-flop 21 is set by the bus prohibition flag 13, so the microprocessor) 2 is set to 130tllll
+ can be identified.

FIG. 4 is a flowchart showing the processing flow of the above embodiment. If there is a data bus use request instruction signal B from the microprocessor 12 (step 41), it is determined whether the bus busy flicker 4 is set or not. Judgment 1 - If f is set, wait for reset, and if it is reset, determine whether there is a bus error signal 18 (step 43), if there is no bus error signal 18, it is normal If there is a bus error signal 18, it is determined whether or not the bus use prohibition flag J3 is 1'' (step 45), and if it is not 1'', the bus nozzle processing is performed (step 46). ), “1°′
If so, a bus use prohibition process that activates the inhibition logic circuit 15 is performed (step 47).

According to the f-tabus control system shown in the above embodiment, there is no need for the microprocessor J2 to check the bus use prohibition flag 13 before outputting the bus use request signal 16, and the bus use prohibition flag '3 is '0
'', it is possible to increase the processing capacity of the microprocessor J2. Therefore, as shown in the flowchart of FIG. The data bus control method of the above embodiment is effective to the extent that one to several instruction steps of the microprocessor are reduced and the number of times the bus is used per unit time is large, unlike the case where the data bus control method is performed prior to outputting a signal.

〔Effect of the invention〕

As explained above, in the data bus control method according to the present invention, each logical unit is controlled by a bus use prohibition flag.
A bus use request suppression logic circuit is provided to suppress bus use requests output from the logic circuit unit requesting bus use to the bus control unit, thereby reducing the processing overhead of the microprocessor. , has an extremely excellent effect on improving the processing efficiency of microprocessors.

[Brief explanation of the drawing]

Fig. 1 is a flowchart of a conventional data bus control method, Fig. 2 is a block diagram showing the configuration of a data processing device, Fig. 3 is a block diagram showing the configuration of a logic circuit unit, and Fig. 4 is a block diagram showing the configuration of a logic circuit unit.
The figure is a flowchart of a data bus control method that constitutes one embodiment of the present invention. 1-1 to 1-n...Logic circuit unit, 2...Data bus, 3...Data bus control unit, 4-1 to 4
-n...Data bus control signal, 11...Logic circuit unit, ]2...Microprocessor, 13...Bus use prohibition flag, 14...Bus busy flip-flop, 15...Suppression logic Circuit, 16... Bus use request signal, 17... Bus use end signal, 18... Bus error signal, addition... Bus error detection signal, 21...
Bus error flip-flop, 22...Bus use prohibition signal, B...Bus use request instruction signal. 13 Figure 3 11

Claims (1)

[Claims] It is composed of a bus control unit that processes bus use request signals from the unit and performs bus control all at once, and each logic circuit unit has a micropro use prohibition flag that outputs the path use request signal and identifies the bus use area. 1. A data bus control system comprising: a bus use request suppression logic circuit controlled by a bus use request suppressing logic circuit to suppress a path use request signal output from a logic circuit unit requesting bus use to the bus control unit.