JPS59215157A - Data transmission system - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by providing the 1st and 2nd means converting 0 or 1 of a binary input data to a prescribed level, converting code by both means and transferring data so as to transmit simultaneously data and clock independently of a transmission speed. CONSTITUTION:An input data is inputted to AND circuits 1, 2, 6 and an NAND circuit 5 of a data transfer system and a clock is inputted to the circuits 1, 2, 6 and an AND circuit 8. Further, an output of the circuits 1, 2 is supplied to a clock and a reset terminal of an FF4, an output of the FF4 is inputted to the circuit 5 and a data terminal of the FF4 and an output of the circuits 6, 8 is supplied to a base of transistor (TRs) 1, 2 respectively. Then, ''0'' of the binary input data is converted to +1, -1 level and 1 is converted to +1, 0 level and when 1s are consecutive, 1 is converted to +1 level and -1 level alternately. The data is code-converted by this conversion and the data is transmitted to transfer simultaneously the data and clock information independently of a transmission speed.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a data transmission method that simultaneously transmits data information and clock information, and does not particularly depend on the transmission speed (b)
The present invention relates to a data transmission system that can easily suppress DC fluctuations when there are consecutive 0's and 1's and can transmit and receive data with a simple circuit.

(b) Prior art and problems As a data transmission method that simultaneously transmits data information and clock information using a circuit that does not depend on transmission speed, conventional technology has changed "0" to "10i, -i" level and l" to "+1. The clock information is extracted by converting to 0'' level and identifying the 0'' and 6+1'' levels, and the data information is reproduced by identifying the latter half time slot of the data with the 0'' and -1'' levels using this clock. However, normally, on the data receiving side, the DC component is removed using a capacitor, and the peak-to-peak amplitude is controlled to be constant using the AGC. works to double the amplitude, and when identifying 1""0" in the data, "l"
It is now incorrectly identified as "all 1", resulting in code identification error bt
arise. For this reason, in the case of this conventional code conversion method, a scrambling circuit which is a continuous same code suppression circuit or a transmission speed is completely increased and if 1" is continuous, all digits are inserted, and if 0 is continuous, 1 is inserted.
It is necessary to use a code conversion circuit for inserting ", which has the drawback of increasing the circuit size. (e) Purpose of the Invention In view of the above-mentioned drawbacks, the object of the present invention is to convert data information using a circuit that does not depend on the transmission speed. An object of the present invention is to provide a data transmission method that can reduce the circuit scale in the case of a data transmission method that simultaneously transmits clock information.

(d) Structure of the Invention In order to achieve the above object, the present invention converts binary input data 0" to 1+1.-1" level to "1"-iz"+1°0" level, and 1” if 1” is consecutive
It is characterized by providing means for converting alternately between the i"+1.0" level and the -1,0" level to perform code conversion and transmit data.The data signal converted by this code conversion is , there are always +l level and -l level within two time slots.
Since it has a level peak, no code error occurs in AGC on the receiving side.

(e) Embodiment of the Invention An embodiment of the present invention will be explained below with reference to the drawings.0 Figure 1 is a block diagram of a transmitter circuit according to an embodiment of the present invention, and Figure 2 is a time diagram of waveforms in each part of Figure 1. In the chart, (5) is the input signal, ノ) is the clock, (C)""(E() is the first
In the figure, Ωc=h point, (I) shows the output signal.

1 in the figure. 2. 6. 8 is an AND circuit, 3 and 7 are inverting circuits, 4 is a flip-flop (hereinafter referred to as FF), 5 is a NAND circuit, 9 is a light emitting element, Tr+, Tr2 is a transistor, R is a resistor, and the value twice that of 2R&[ shows resistance.

0101111001110 as shown in younger brother 2 diagram (4)
An explanation will be given taking as an example a case where the data of 1 is input and the clock shown in FIG. 2(B) is supplied.

The input data shown in the 21st prisoner is input to the AND circuit 1 via the inverting circuit 3, and also to the AND circuit 2 and the NAND circuit 5.
Enter. Also, the clock shown in FIG. 2(B) is input to the AND circuit via AND circuits 1, 2.8 and inverting circuit 7! r6
to use human power. When the AND circuit 1 takes the logical product of the two inputs, the output is the signal shown in Figure 2 (C), and this signal 1
Input to the reset terminal of FF4. On the other hand, AND circuit 2
When the two inputs are ANDed, the signal shown in FIG. 2 (2) is obtained, which is input to the clock terminal of this signal 'kFF4. In FF4, until it is reset by the signal in FIG. 2(C), the signal shown in FIG. The signal shown in (g) is obtained. When this signal and the input signal are ANDed in the NAND circuit 5 and inverted by 9, the signal shown in FIG. 2 (G) is obtained. When the signal shown in Fig. 2 (I) and the clock shown in Fig. 2 (B) are logically multiplied by the AND circuit 8, the result shown in Fig. 2 (G) is obtained.
The signal will be as shown in . On the other hand, when the signal obtained by inverting the clock shown in FIG. 2(B) by the inverting circuit 7 and the input signal of FIG. 2(4) are ANDed by the AND circuit 6, the signal shown in FIG. 2(0) is obtained. Become. The signal shown in FIG. 2 I is input to a transistor Tr+ having a resistor 2R' between its emitter and ground, while the signal shown in FIG. When the signal input to the transistor Tr is 1, the light emitting element 9 emits light corresponding to the θ level, and when the signal is 0, it does not emit light.

(equivalent to - level) Also, when the signal input to transistor Trt is 1, the light emitting element 9 emits light corresponding to +l level, and when it is 0, it does not emit light (equivalent to - level) 0 This is between the emitter of transistor Tr2 and the ground. This is because the resistance [R] is 2R, and the resistance between the emitter of the transistor Tr1 and the ground is 2R.

Therefore, the light output from the light emitting element 9 is as shown in FIG. 2 (I). The output waveform shown in FIG.
When the binary data in Figure (5) is input, it is converted to 0"-(("+1°-1" level to 1"i"+1.0" level, and if 1" is consecutive, 1" is changed to +1, 0” level and -1
, 0'' level. Furthermore, the circuit shown in FIG. 1 has no part that depends on the transmission speed.

FIG. 3 is a block diagram of a circuit of an embodiment for receiving data in the data transmission system of the present invention, and FIG. 4 is a time chart of waveforms of each part in FIG. 3, where (4) is an input signal, (B) to ( 6)
(b) indicates the signal at points b-h and m in FIG. 3, υ indicates the reproduced clock, and (v) indicates the reproduced output data.

In the figure, 10 is a light receiving element, 11 is an automatic increaser, and 1
2.13 is a comparator, and comparison voltage V+, V- is V of the 41st prisoner.
This is an intermediate value between +l level and θ level corresponding to + and V-, and an intermediate value between 0 level and 1 level. 14? t
6 is a rising detector, 15° 17 is a falling detector, 18
．． 20 is an AND circuit, 19.21 is an inversion circuit, 22.2
3 is an OR circuit, 24.26 is an FF, and 25 is a delay circuit.

The transmitted optical signal is converted into a stain signal by the light receiving element 10 and amplified by the amplifier 11 to become the signal shown in the 41st column. This signal is inputted to the comparator 12.13, compared with the respective comparison voltages V+ and V-, and identified as 1, outputting the signal shown in FIG.
The falling edge 9 is detected by the falling edge υ detector 15, which is input to the OR circuit 23, and outputs the signal shown in FIG. 2
The signal is inputted to 0 and also inputted to the OR circuit 22. ml1 diagram (Q
The rising edge of the signal is detected by the rising edge detector 16, and the fourth signal is detected by the rising edge detector 16.
The signal shown in figure (g) is fully output, and one falling edge detector"7
The falling Jt is detected at 0 and outputs the signal shown in the fourth diagram, which is input to the AND circuit 20.The AND circuit 18.20 performs the logical product of the two input signals, respectively. (
The signals shown in J) are obtained and input to OR circuits 22 and 23, respectively. The OR circuits 22 and 23 each receive the logical sum of the two input signals and the signals shown in FIG. F
At f+' 24, it is reset and set by the signals shown in FIG. This clock has an occupancy rate of 50 rice cakes. On the other hand, the clock shown in Figure 4 (g) is F
When the transmission speed is maximum, the signal shown in FIG. The signal shown is input to the D terminal of the FF 26.

If the phase of the input signal shown in FIG. 4 is identified using the clock shown in FIG. 4, a reproduced data signal as shown in FIG. 4 is obtained.

The circuit shown in FIG. 3 also has no part that depends on the transmission speed of the received data.

In this way, even if the data input to the transmitter circuit is 1" continuous, the DC fluctuation will be slight and a peak of +1.-Level will occur every time slot, so the AGC on the receiver side will be able to control the amplitude. By doubling the code, code errors do not occur, and a scrambling circuit or a code conversion circuit that increases the transmission speed and inserts a different code is not required, and the circuit size can be reduced.

(f) Effects of the Invention As explained in more detail, the present invention has the effect of reducing the circuit scale in the case of a data transmission system that simultaneously transmits data information and clock information using a circuit that is unrelated to the transmission speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitter circuit according to an embodiment of the present invention, FIG. 2 is a time chart of waveforms at the bottom of FIG. 1, and FIG. 3 is a block diagram of a receiver circuit according to an embodiment of the present invention. FIG. 4 is a time chart of waveforms at various parts in FIG. 3. 1 in the figure. 2. 6. 8. 18. 20 is an AND circuit, 3, 7. 19. 21 is an inverting circuit; 4. 24
．． 26 is a flip-flop, 5 is a NAND circuit, 9 is a light emitting element 1. ig is a light receiving element, 11 is an amplifier, 12.13
14 and 16 are rising 9 detectors, 151 t7 is a falling detector, 22 and 23 are OR circuits, and 25 is a delay circuit. Mine 4 Figure (1) (D) (Ni) (M) (F) and tJn (1) U winter 4
− Hear

Claims (1)

[Claims] In a data transmission method that simultaneously transmits data information and clock information, O'' of binary input data is set to ``+1''. -1”
level to 1"t-"+1.0" level, and l
If `` is consecutive, ``1'' is ``+1.0'' level and ``-
1. A data transmission system characterized by providing means for alternately converting into i and o'' levels, and transmitting data after code conversion by said means.