JPS59215127A - Signal synthesizing circuit - Google Patents

Abstract

PURPOSE:To lower operating input frequency, to simplify a circuit constitution and to reduce power consumption by adjusting an output pulse width transmitted from a counter every time a delay compensating counter counts up. CONSTITUTION:A signal generator 10 transmits a reference signal S11, a signal S2 that is inverted signal S1, a signal S3 that is advanced in phase signal S1 by 1/4 period, and a signal S4 that is inverted signal S3, to a signal input circuit 11. The signals S1-S4 are selected cyclicly from the circuit 11, and fed to the post-stage by the control of an input signal selecting circuit 13. A counter 12 counts decimally an output of the circuit 11 and also outputs a reference signal. Further, a count-up signal of the counter 12 is fed to a delay compensating counter 14, which corrects the delay in the output pulse outputted from the counter every time the counter 14 counts the 25 signals. Then, the frequency of the input pulse signal is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a signal with a predetermined frequency that cannot be obtained directly from the output signal of a frequency division stage that completely divides the signal from an oscillation source, by dividing the signal from an oscillation source into the lowest possible frequency of the frequency division stage. The present invention relates to a signal synthesis circuit that synthesizes using frequency output signals, and more specifically, it is used to completely synthesize reference signals such as 100 Hz used in stopwatches.

PRIOR ART Conventionally, in order to obtain a reference signal to be input to a stopwatch counter in a sub-clock, etc., a predetermined number of clock pulses output from a frequency dividing stage are masked at regular intervals. Alternatively, there is a method of generating a reference signal of a fixed period in a pseudo manner by counting all the constant number of pulse signals of cylinder frequency.

FIG. 1 shows a conventional signal synthesis circuit according to the former method, which uses a 1024HzO frequency divided output signal to generate a stopwatch counter standard No. 1g (100H2).
This shows the case of generating .

In FIG. 1, reference numeral 1 denotes a pulse generation circuit consisting of a flip-flop and a logic element, which generates a signal of 1000H2 from a signal pulse of 1024H2. A counter 2 divides the output pulse of the pulse generating circuit 1 into a 100 Hz signal. Further, FIG. 2 is a timing chart showing the output waveform of the a''-n portion shown in FIG. 1.

In the circuit with the above configuration, when the IL]24H2(7) pulse signal is input to the pulse generation circuit 1, five pulses are generated every 8Hz as shown in FIG. 2(h) to (1) among the signal pulses. As a result, a pulse corresponding to 1000 Hz (1000 Hz) is extracted from the output terminal of the pulse generation circuit 1, that is, the output side of the NAND gate NAND, as shown in FIG. If you input and divide the frequency, the output terminal of counter 2 is 0 [TT is 100Hz
A reference signal will be sent out.

However, the reference signal obtained by such a conventional method has a large measurement error and is not suitable for a reference signal synthesis circuit for a stopwatch, etc., which requires highly accurate measurement.

FIG. 6 shows a conventional signal synthesis circuit using the latter method. In the figure, 1 is the third counter,
4 is the 20th counter, and a ” of the first counter 5
The output waveform of the -h portion is shown in FIG. 4A, and the output waveform of the 1 to q portions of the second counter 4 is shown in FIG. 4B.

In the conventional signal synthesis circuit as shown in Fig. 6, y
As is clear from the operation timing chart in Figures ah and B, the first counter 3 counts 4096H2 pulses, and every time the first counter 3 counts 41 pulses, the number of pulses in Figure 4A (as shown in hl)
This output pulse (1) is counted by the second counter 4, and the counting operation is repeated 99 times, and at the 100th time, the first counter 3 counts the 4096 Hz pulse m3. When I did,
The signal (1) in Fig. 4B is added to the first counter 6 so as to send out one pulse, thereby giving a pseudo value of 100 H.
This is to generate standard No. 16 of z.

In the signal synthesis circuit of this type, the measurement error can be reduced somewhat compared to the method shown in FIG. 1, but as is clear from FIG. As the number of components increases, the number of circuit components becomes extremely large, which is disadvantageous to the economy. 1. Using all high frequency signals of 4096 Hz as the reference input signal means that the number of bits of the counter that counts it,
That is, the number of flip-flops increases, resulting in an increase in power consumption.

Oscillators that are the basis of timekeeping such as electronic watches generally have 2
n) (Z crystal oscillator is used, which makes it impossible to generate a perfect 100Hz signal, but
When trying to obtain a 100 Hz signal using the counter as described above, the higher the frequency of the reference input signal, the higher the accuracy of the generated pseudo 100 Hz signal. An example of this is as follows.

', /4o96X41 =1o,o 09765m5e
c1/131°72X1310=10.0021361
However, as mentioned above, it is undesirable to increase the frequency of the input signal used in terms of power saving, and the higher the frequency used, the more the counter that counts J1 becomes The number of bits (number of flip-flops) will increase. Furthermore, 41. (If a frequency of HZ is used, a 100H2 signal with an extremely small error can be realized as shown in the example above, but this is only from the viewpoint of calculation, and in reality, the operating speed of the elements constituting the counter is This poses a problem, and furthermore, the operation of the circuit becomes unstable, making it impractical.

This means that when 100H2 signals are synthesized using a counter configuration, the most suitable frequency to use in order to obtain a 100Hz signal with higher accuracy than in practice is 4096Hz, and even if a higher frequency is used, it will not work. This means that signal synthesis with higher precision than above cannot be expected. and 1ζ, 4
There is a desire for a signal synthesis circuit that uses a circuit with as few components as possible at a frequency lower than 0.096 Hz and that does not provide the same accuracy as when using 4096H2f.

OBJECTS OF THE INVENTION The present invention has been made in view of one point, and includes at least four types of input pulses having the same frequency and different phases, which are sequentially counted by a predetermined number by all 4n counters,
A system in which the output pulses sent out each time the human pulse signal counts up is counted by a money loss compensation counter, and the width of the output pulses sent out from the counter is adjusted every time the delay compensation counter counts up. It is an object of the present invention to provide a signal synthesis circuit in which the frequency of input signals used is lowered, and the circuit configuration is simplified and power consumption is reduced.

Embodiment 2 Structure and operation of the invention Hereinafter, a specific embodiment of the invention will be described based on the drawings.

FIG. 5 is a functional block diagram showing an example of the @-type circuit of the present invention, in which 10 is a signal generation source for generating the reference pulse Ig used for generating signals such as 1o OI (z). And from the 10th of this complaint, 1024 H
z pulse signal S1 and inverting this, fcl 024
A pulse signal S2 of Hz and a pulse signal S3 of fr-102aHzM by advancing the phase of the pulse signal S1 by A period,
and 1 02411 z which is the inversion of this pulse signal S3
The M pulse signal S4 is sent out.

Each pulse signal S1 to S4 from the signal generation source 10,
One of the pulse signals is selected and sent to the counter 12. According to the selection command from the input signal selection circuit 13, the pulse I5E is output to the IHA input circuit 11.
S1 to S4i - Sequentially and cyclically selected and transmitted.

The f-counter 12 is composed of a decimal σ) counter that counts each pulse signal selectively sent out from the signal input circuit 11, and counts at the falling edge of the input pulse signal. (The pulse that is output in synchronization with the falling edge of the i signal is input to the counter 12 as a reset pulse of the counter 12, while the pulse that is output as a reference signal of the desired composite 1g square, for example, 100-Hz) Further, the output pulse from the decimal counter 12 due to the count up is sent to the lagging arm counter 14.The lagging f1 compensation counter 1411''t2 decimal counter 1
It has a function of supplying a finger for selecting a reference pulse signal to the selection circuit 16, and counts the output pulses by a predetermined number, that is, 25. It sends out a signal for delay correction every time. And delay compensation counter 1
The delay correction signal from 4 is applied to a pulse width adjustment circuit 15, and this pulse width adjustment circuit 15
, the delay compensation counter 14 counts up, that is, 2
Every time the fifth output pulse is sent out, the width of the 25th output pulse is adjusted so that the time delay (counting error) caused by using the full 1024Hz reference pulse signal becomes zero. .

Furthermore, the delay compensation counter 14 and the pulse width adjustment circuit 15 are configured to receive one of the pulses IN numbers 81 to S4 selected in response to a selection command from the input signal selection circuit 16.

FIG. 6 shows a specific circuit configuration example of each functional block shown in FIG. It is composed of clock gates G5 to G8 which selectively send one of pulse signals S1 to S4 to a compensation counter 14 and a pulse width adjustment circuit 15. In addition, the decimal counter 12 is connected to a Nant gate N A which receives the signal ``Nokurusu Gogo'' from the input circuit 11 as an input.
N D 1 and this knot gate N A N D 1
The output of the count flip-flop FF1~
F F' 4 and this Noritsubu flop If"F'
The Q output of 2 and FF'4 is set to one hand, and the pulse width is 1.
4' The output information from the J circuit 15 is the flip-flop FF5, which is connected to the other input, and the Noritsubu flop Ii.
F' 5 output (Russ (101JHzl/) standard 1S
It is composed of a NOT gate NOT1 which inverts the signal (corresponding to the number), and a NAND gate NAND2 which is operated by the output number 1 of the NOT gate NOT1 and resets the flip-flops FF1 to FF4. Furthermore, the above-mentioned delay, F'1. The compensation counter 14 includes a flip-flop F that counts all the output pulses of the decimal counter 12.
F6--FF10 and these flip-flops FF6, F
A flip-flop FF11 which receives as inputs the outputs of F'jl and plt'10, and a flip-flop FF11 which receives the output signal of NOR1 and the pulse signal from the above input circuit 11. and flip-flop FF
9. AND gate AND with Q output of FFID as input
And this AND gate AND and flip-flop 1F
NOR gate N0R2 with all output signals of lt'11 as input
, a NOT gate N0T2 that inverts the output signal of the NOR gate N0R2, and a NOT gate N0T2 that inverts the output signal of the NOR gate N0R2, and a NOT gate N0T2 that inverts the output signal of the NOR gate N0R2;
It is composed of a knot gate N0T6 and a NAND gate tlJAND3 which are added to F6 to FF10.

! ! The pulse width adjustment circuit 15 is connected to the signal input circuit 1.
a NAND gate NAND4 which receives the selection pulse signal from 1 and the output signal of the NOR gate N0R2; a NAND gate NAND5 which receives the output signal of the NOT game NOT2 and the pulse power of 1024; and both NAND gates NAND4 and NAND5. Furthermore, the input signal selection circuit 13 is controlled by the Q and Q outputs of the flip-flops FF6 and FF7 of the delay compensation counter 14, and Kuro7ri'r'-toC
)1~G8f: Controlled Noah gate N0R5~NOR
6. Next, the operation of the signal synthesis circuit of the present invention constructed as shown in FIG. 6 will be explained with reference to the timing chart shown in FIG.

At the start of 100HzL71 signal synthesis, since the delay compensation counter 14 has been reset, its flip-flop FF6. The Q output of F'F7 is °'■・'', so the output of NOR3 of the input signal selection circuit 16 becomes "H" level (;7+,'
(see f in Figure 7), open clock gate 01, ()5. In such a state, the Nando game with a decimal counter of 12) NA
The other input of NI:l goes from +t IJn level to “1(
” level, 1024HzM from the signal input circuit
The signal shown in FIG. 7(,) appears on the output side of the NAND gate NAND1 in response to the pulse signal s5 of 10
The digit counter 12 counts 1111 times. Along with this counting operation, a signal shown in FIG. 7(b) appears at the Q output of flip-flop FF2. Then, at the moment when the 10th pulse of the input pulse signal 530 falls, 1
The pulse appearing at the Q output of the flip-flop FF4 of the 0-base counter 12 falls as shown in FIG. 7(c). At this time, one input side of the flip-flop FF5 of the decimal counter 12 is connected to the Id pulse width adjustment circuit 15.
Since the signal shown in 7i1 (cl) is applied to the output terminal 12a of the decimal counter 12, it rises at the falling edge of the 10th pulse of the input pulse signal -]s3, and the pulse width adjustment circuit A pulse as shown in FIG. 7 (θ) that falls at the same time as the No. 15 output pulse rises, that is, an output pulse that generates the entire 100 Hz reference signal is sent out. At the same time, the output pulse cN'j is applied to the reset terminal of each flip-flop F'F1 to FF4 through the NOT gate N0T1 and the NAND gate NAND2i, and the decimal counter 12i is reset. is output to
Upgrade the contents from 0 to 1. As a result, when the delay compensation counter 14 counts the output pulses from the decimal counter 12, the input scenery selection circuit 1NOR4 is selected by the single count operation, and its output "(fn 7) 1 as shown in (g)
By setting it to 'H''', the clock gates G2 and 06 of the signal input circuit 11 are opened.

At this time, the Noah gate kJ O of the delay compensation counter 14
The output of R2 j + (1:, as shown in Fig. 7 (, +)'
The output becomes "Tj" as shown in FIG. The output pulse of 1024 Hz k, 1 during the period when the pulse signal S5 of It becomes a cutting waveform.

On the other hand, as the retard supplementary 1 award power wanta 14 counts 1 pulse, the 1024 Hz pulse signal S1 becomes 10
When the 10th pulse signal S1 is input to the forward counter 12 and falls at 9, the output pulse of the counter 12 rises, and at that moment the content of the delay compensation counter becomes 2, and this time the 1024 Hz pulse Signal S1 is 1L
”, the output pulse e is maintained at ”H'f/C, and the second output pulse with the timing waveform shown in FIG. 7(e) is sent to the output terminal 12a of the counter 12. will be done.

Similarly, when the delay compensation counter 14 counts the second output pulse, the output of the NOR gate N0R5 of the input No. 1B selection circuit 16 becomes tl HM, opens the clock gate G5.07, and the pulse signal of 11024H2 is output. Input S4 into the decimal counter 12. Then, when the 10113 counter 12 counts 10 pulse signals S4 and sends out the output pulse e, the delay compensation counter 1
The content of 4 is further increased by 1, which makes it 1024Hz
The NOR gate N0R6 is controlled so that the pulse signal S2 is input to the decimal counter 12, and the clock gate G4
．． Open G8. That is, each time one output pulse is sent out, the reference pulse signal input to the decimal counter 12 is
4(1024H2M)-+81 These steps are repeated until the delay compensation counter 14 reaches the count-up state.

Note that the moment the output pulse e falls and the input pulse 43 that is next input to the decimal counter 12 thereafter
The timing relationship with the first rise 9 of ~s4 is 0.24 m crowns after the fall of the output pulse θ, that is, 1024
The input pulse signal starts to rise at the moment when a period of 1/4 Hz has elapsed. This timing relationship is such that when each pulse j:f output i91 to S4 is selected by the input signal selection circuit 13, correspondingly, a pulse signal of ID 24Hz is selected at 7'L every quarter period. By inputting the signal to the delay compensation 11γ counter 14 and the pulse width adjustment circuit 15, the 100Hz signal synthesis circuit is kept constant without changing during operation.

By the way, in the above repetitive operation, the time from the moment one output pulse falls until the next output pulse falls, that is, the period of the output pulse is approximately 10.01 m5ec.
Therefore, if the above operation is simply repeated, the output pulse will lag behind 100I (Z) as the operation time becomes longer.The delay compensation counter 14 corrects this delay, and its operation will be described below.

When the delay compensation counter counts 24 output pulses from the decimal counter 12, it sends a signal to the pulse adjustment circuit 15 to wait for the 25th output pulse.At this time, the output of the delay compensation counter 14 jld Figure 7 (j
) as shown in < -(L # level υ, and accordingly the output becomes "■" as shown in Figure 7 (k). In this state, 25 shots are fired as shown in Figure 7 (Q). When the second output pulse rises, this output pulse remains at the "Hl level" for a period when the 1024Hz pulse signal S2 is "L"', that is, for a period of one-fourth of 1024H2 after the output pulse rises. When the 1024Hz signal rises, the output pulse falls.Therefore, the pulse width of the 25th output pulse θ is half of the previous output pulse width, as shown in Figure 7 (,). At this time, 2
Naturally, the contents of the delay compensation counter 14 will change 1ffii after the rise of the fifth output pulse, but in order to prevent this change from affecting the above operation, the output J of the delay compensation counter 14, In other words, the output j of the delay compensating power wanton 14 is kept at the "L" level, and the outputs ki and i are kept at the "H" level.

In this way, from the fall of the 24th output pulse, 2
The falling time of the 5th output pulse is approximately 9.7 at 9 necks.
7m5ec, the time from when the 100Hz signal synthesis circuit starts operating until the moment when the 25th output pulse falls is 0.25cm, which is the moment when the 25th output pulse falls. The delay in the output pulse up to il, that is, the counting error, is all canceled, and this counting error canceling operation is performed every quarter period of one second.

Well, the width of the 25th output pulse is half the width of the previous output pulse, so the falling edge of the output pulse, which had been kept constant until then, becomes 9, which is input to the next decimal pulse 12. It is necessary to select the input pulse signal to the decimal counter 12 so that the timing does not deviate from the first rise of the input pulse signal. In this case, the delay compensation counter 14 may be reset to set its contents to 0 in synchronization with the rise of the 25th output pulse.

Note that in the above embodiment, a case has been described in which four types of input pulse signals S1 to S84 having the same frequency and different phases are used to synthesize the reference signal, but more types of input pulse signals may be used. Also, its frequency is 1024Hz
The present invention is not limited to 100 Hz, and can also be applied to cases where all reference signals other than 100 Hz are generated. Furthermore, the count contents of the counters 12 and 14 are changed according to the frequency of the generated reference number 100.

Effects of the Invention As described above, according to the present invention, at least four types of input pulse signals having the same frequency and different phases are sequentially counted by a predetermined number by a counter) L, -'f: (1)
The output pulse sent out every time the input pulse signal counts up is saved by a delay compensation counter, and the output pulse width fr sent out from the counter is adjusted every time the t21 delay compensation counter counts up. Since this method corrects the word count error, it is possible to lower the frequency of the input pulse fi used to generate the output pulse, that is, the reference signal, and accordingly, the frequency of the input pulse fi used to generate the output pulse, that is, the reference signal, can be lowered. The number of circuit elements is reduced, making it possible to simplify the circuit configuration to njj, and also to reduce energy consumption.

[Brief explanation of drawings]

Figure 1 is a logic circuit diagram showing a conventional signal synthesis circuit. Figure 2 is a timing chart showing the operating waveforms of each part. Figure 5 is a logic circuit diagram showing another example of the conventional signal synthesis circuit. 4(A) and 4(B) are timing charts showing the operating waveforms of each part, and FIG. A logic circuit diagram showing an example of the configuration, and FIG. 7 is a timing chart showing operation waveforms of each part in the present invention. 10...Signal generation source 11...Signal input circuit 12. ...10i counter 15...Input signal selection circuit 14...Delay compensation counter 15...Pulse width adjustment circuit board

Claims (2)

[Claims] (1) An f1 generation source that generates at least four types of input pulse signals with the same frequency and different phases, a Shikotan input circuit that receives each input pulse signal from this double hoof generation source, and this fg large input Each human power pulse 18 taken into the circuit
An input signal selection circuit that cyclically selects and sends out the numbers in a predetermined order, and counts all of the individual couplers 1B that are sent out in order from the No. 16 input circuit, and each time it counts up, the desired station 1732 number is selected. A counter that sends out an output pulse to represent 'lF' + 'C', and a counter that counts the output pulse of this counter by 1. An input pulse signal selection command is given to the input signal selection circuit, and the output pulse is set to a predetermined value. A delay compensation counter that sends out a signal for correcting the delay nine every time a number is counted, and an output No. 19 from this delay compensation counter that is operated to adjust the output pulse width of the counter every time the delay compensation counter counts up. A signal synthesis circuit consisting of a pulse width adjustment circuit that compensates for counting errors. (2) At least four types of input pulse signals include a first input pulse signal having a desired frequency and a second input pulse signal having the same frequency as the input pulse signal but different phases;
2. The signal synthesis circuit according to claim 1, comprising third and fourth input pulse signals obtained by completely inverting both of the input pulse signals.