JPS59214774A - Peak detector - Google Patents

Abstract

PURPOSE:To eliminate the outputting of a false peak voltage by providing a slope detection circuit for discriminating the leading edge and the tailing edge of a signal to be observed to reset a positive/negative peak holding circuit at a positive or negative peak point. CONSTITUTION:A slope detector 400 and a reset pulse generation means 401 are provided. Even when a positive peak holding circuit 103 is reset to a false voltage E6 at the time T4, the hold voltage is reset to a negative peak at the time T4' and the circuit 103 holds a normal peak voltage E9 at the time T6, hence not a false peak voltage. The negative peak holding circuit 104 does the same. Thus, no false voltage will be outputted for the sample holding 106.

Description

[Detailed description of the invention]

<Technical field of the invention> This invention is applicable to, for example, digital processing v4! Regarding a peak detection device suitable for application to a type spectrum analyzer, if
Furthermore, it is an object of the present invention to provide a peak 4 detection method that can detect the peak i1σ of the observed signal without error. <Background of the Invention 1j1> Conventionally, a spectrum analyzer (on the crotch) is configured with an analog circuit, and is designed to display, for example, the frequency spectrum of the observed signal on a cathode ray tube. It has the disadvantage that the displayed waveform cannot be stored in memory.For this reason, recently, the observed signal has been converted to high-speed A-DI and has been converted into a digital ray that can be stored in memory. -A digital processing type spectrum analyzers that perform A conversion and display on cathode N tubes are becoming mainstream.Digital processing type spectrum analyzers can store waveforms as described above and are easy to perform arithmetic processing. It is possible to provide a spectrum analyzer with high value because it can immediately display waveforms corresponding to the difference or sum of observed waveforms.
A sampling circuit and a hold circuit are provided in connection with the -D i conversion U-+j+ operation. The sampling frequency of the sampling circuit is switched in relation to the sweep speed of the spectrum analyzer. These nine filters allow the observed signal to be sampled finely so that at least the positive and negative peaks can be sampled without exception. If the sampling period is extremely short compared to the period of the observed signal, it is possible to sample all the positive and negative peaks of the observed signal and perform A-Df[. However, as the rumbling period and the period of the observed signal become closer, it becomes difficult to reliably capture and sample the positive and negative peaks. For this reason, a structure is generally adopted in which positive and negative peak bold circuits are provided in the preceding stage of the sampling circuit, and the peak and bottom of the observed signal are reliably captured and captured by the peak hold N circuits. This part is generally called a peak detection device. <Description of Prior Art> Figure 1 shows a conventional peak detection device of 4111 type. 101 in the figure is observed n! ++ Breakdown given to this input terminal 101 showing the input terminal of WW No. 102

[Rules/faith-
The signal 102 is input to both the positive peak hold circuit 103 and the negative peak hold circuit 104. The outputs of the positive and negative peak hold circuits 103 and 104 are sent to the selection circuit 10.
5, one of them is selected and taken out, and held in the sample bold circuit 106. The output of the sample bold circuit 106 is output terminal 1
07, and is supplied from the output terminal 107 to a converter (not shown). 108 is the selection circuit 105? +71. The control circuit for control is shown. The control circuit 108 includes a voltage comparator 109 and a D-type flip circuit 111 that takes in the comparison output of the voltage comparator 109 as a logical value. A voltage comparator 109 compares the voltages of the output of the sample bold circuit 106 and the observed signal 102 in magnitude. The hold output of the sample bold circuit 106 is applied to the inverting input terminal, and the observed signal 102 is input to the non-inverting input terminal. A sampling pulse 202 shown as m2gB is applied to the clock terminal CK of the D-type flip 70 tube 111. If the observed signal 102 shown in FIG. 2A is input to the input terminal 111, the output terminal Q of the D-type flip-flop 111 outputs a positive-phase rectangular wave signal 204 shown in FIG. This positive phase rectangular wave signal 204 is applied to the selection circuit 105. The selection circuit 115 selects the positive phase rectangular wave signal 204 as 1.
1 logic selects the positive peak hold circuit 103,
It operates to select the negative peak hold circuit 104 when the logic is L. 112 indicates gate means. This gate means 112 is composed of two AND gates 113 and 114,
1] type flip-flop 1 in one AND gate 113
11 output terminal Q is given a negative phase rectangular wave (r' as number 204, and the other AND gate 114 is connected to a D-type flip 70 tube 1.
A positive phase rectangular wave signal 204 is provided at the output terminal Q of No. 11. The input sieve 1 of each other of these AND gates 113 and 114
A reset pulse 203 shown in FIG. 2C is applied to the child. The pulse 205 shown in FIG. 2E is a reset pulse output from the computer 1-13. Further, a pulse 206 shown in FIG. 2F is a reset pulse output from the AND gate 114. The output pulse 205 of the AND gate 113 is applied to the reset terminal it of the positive peak hold circuit 103, and the output pulse 206 of the AND gate 114 is applied to the reset terminal R of the negative peak hold circuit 104. <Description of operation of prior art> In the above-mentioned jtQ structure, when the sampling pulse 2.02a is input at time T1, at this time TI, the output signal 204 of the output terminal Q of the D-type flip-flop 111 is
is L Afi principle. Therefore, the selection circuit 115
selects the negative peak hold circuit 104, and the sample hold circuit 106 samples and holds the hold voltage E1 held by the negative peak hold circuit 104. Next, when the sampling pulse 202b is applied at time T2, the output signal 204 of the D-type flip 70 tube 111 is H logic, so the selection circuit 11
5 selects the positive peak hold circuit 103. Therefore, the sample hold circuit 106 samples and holds the voltage E2 held by the positive peak hold circuit 103. When the sampling pulse 202C is applied at time T3, the output signal 204 of the D-type flip-flop 111 is at L logic. Therefore, the selection circuit 105 selects the negative peak hold circuit 104 and takes the hold voltage E3 into the sample hold circuit 106. When the sampling pulse 202d is applied at time T4, the selection circuit 105 selects the positive peak hold circuit 103 because each output 204 of the D-type flip-flop 111 is H logic. Therefore, the sample hold circuit 106 holds the hold iil! held by the positive peak hold 1u path 103. ,
Sample and hold pressure E4. 11. Sampling pulse 202e at lf point T5
When Ji is obtained, at this time, the D type flip-flop 11
Since the output signal 204 of 1 is L i = logic, the selection circuit 1
05 selects the negative peak hold circuit 104. Therefore, the sample and hold circuit 106 samples and holds the voltage E5 held by the negative peak bold circuit 104. <Disadvantages of Prior Art> The explanations up to 5 describe normal operations. In other words, the sample and hold circuit 106
．． Ta, T4. At Ts, sample and hold the hold voltages ftt~Es of the positive and negative peak hold circuits 10:3 and 104, and apply the sample and hold voltages to A-D.
Since it is supplied to a converter, it is converted from A to D and then converted to v - A again, and the waveform 207 shown by the dotted line in FIG. 2 is reproduced.
The positive and negative peaks (direct and positive) of the spectrum are reproduced very well. The drawback of the conventional method occurs at the next sampling point Ta. When the sampling pulse 202f is applied at the cutting point T6, the signal 204 is ■(After becoming logic, the selection circuit 105 is a positive peak hold circuit 103
Select. The positive peak hold circuit 103 is activated at time T4.
A reset is applied by a reset pulse 203a applied immediately after , and as a result of the reset, the positive peak hold circuit 103 holds the voltage E6 in the middle of the fall of the voltage U++I<8. This results in the sampling time T6 of the method? Therefore, the sample and hold circuit 106 samples and holds the city 1 pressure E6. Immediately after this sample and hold operation, the positive peak hold circuit 103 is reset to voltage E7 by a reset pulse 205. In the end, the conventional peak detection device outputs a false peak voltage E6 immediately after a spectrum with a large peak value, and a false peak voltage E6 is output on the cathode ray tube as shown by the dotted line in Figure 2).
・Ram is displayed. FIG. 2 shows a considerably enlarged time axis. In reality, the display is as shown in Figure 3.
, a false peak spectrum 302 is displayed next to a truly large peak spectrum 301. <Object of the Invention> The present invention aims to provide a peak detection device that does not output the false peak voltage E6 shown in FIG. <Ammonium sulfate of the invention> In this invention, a slope detection circuit is provided to distinguish the rising and falling sections of the observed signal, and at the positive peak point, the negative peak hold circuit is reset, and at the negative peak point, the slope detection circuit is reset. tl is configured to reset the peak hold circuit. With this configuration, the positive peak hold circuit performs the reset operation at least at the negative peak point immediately before performing the peak hold operation, and the negative peak hold circuit 104 performs the reset operation at the negative peak point immediately before performing the peak hold operation. Since the reset operation is performed at the time, the positive and negative peak hold circuits 103 and 104 do not output false peak pressures. Therefore, by providing the peak detection device of the present invention in front of the A-D conversion means of a digital processing type spectrum analyzer, it is possible to eliminate the inconvenience that a false peak waveform is displayed immediately after a waveform having a large peak value. I can do it. <Embodiment of the Invention> FIG. 4 shows an embodiment of the invention. In FIG. 4, parts corresponding to those in FIG.
0 and a reset pulse generating means 401 that generates a reset pulse at the positive and negative peak points immediately after sampling based on the detection output of the slope detector 400. The configuration is such that the positive and negative peak hold circuits 103 and 104 are reset by adding the reset pulse used from the above. Therefore, according to the present invention, in addition to the reset operation by the reset pulse 203 explained in FIG. The negative peak bold circuit is reset by the pulse output at the positive peak point after the tumbling operation iM. As shown in Figure 5, even if the positive peak hold circuit is reset to a false '1[I-pressure E6' at time T4, the positive peak hold circuit at time T4' will be The hold voltage of the peak hold circuit is reset to a negative peak value. Therefore, at time T6, the positive peak hold circuit 103 holds the normal peak voltage E8 and does not hold a false peak voltage. The details will be explained below. FIG. 6 shows the structure of the slope detector 400 and the reset pulse generating means 401. The slope detection circuit 400 is provided with an operational amplifier 601 on the front stage side. The observed signal 102 is applied from the input terminal 101 to the non-inverting input terminal of the operational amplifier 601 . Same as the inverting input terminal of the operational amplifier 601 iL'l ff1jb 5f
A charging/discharging capacitor 603 is connected between the point 602 and the charging/discharging capacitor 603 . Also, a diode 60 is connected between the output terminal and the inverting input terminal.
4 and 605 are connected. A voltage comparator 606 constituted by an operational amplifier is provided at the subsequent stage of the operational amplifier 601. The output of the operational amplifier 601 is applied to one input terminal of the voltage comparator 606, and the output from the input terminal 101 is applied to the other input terminal. Observation (S No. 10
Give 2. Note that the circuits 607 and 608 connected to the input (411) of the voltage comparator 606 operate as filters for noise removal. According to the circuit structure of this slope detection circuit 4000, the input ☆
;If a triangular waveform side wave 102 as shown in FIG. 7A is given to the tmiko 101, the operational amplifier 6
The output voltage of 01 changes as shown by the dotted line 701 in FIG. 7A. That is, when the observed signal 102 is on an upward slope, the operational amplifier 601 charges the capacitor 603 to 1 through the diode 605. This Pukome Mouse Computing Amplifier (
The output of iol is 1) 1 pressure is supplied to the human powered singer 101 as shown in Figure 7A'P) J RR61! Ii No. 102 No'11.7f f Retire ode 605
becomes higher by the forward voltage drop Vox. On the other hand, when the output signal 102 is in the descending slope, the operational amplifier 601 attracts the photoelectric pressure "11-j" to the capacitor 603 through the diode 604. As a result, the output voltage of the amplifier 601, ``θ, pressure is shown at point C in Figure 7 A, J: '>Caill's message.
1102o'rlx. It is lower than the current by the forward voltage drop VD2 of the diode 604. In this way, the F(;1 voltage at the output terminal of the operational amplifier 601 changes by becoming larger or smaller than the observed signal 102 at the rising slope and falling slope of the observed signal 1(2). output and riM
By comparing the 6111 signal 102 with the voltage comparator 606, the stain pressure comparator 606 detects when the load 1 measurement/1 month 102 moves from the upward slope to the downward slope and when the downward slope changes, as shown in FIG. 7B. A rectangular wave 702 that transforms when transitioning from to an upward slope is 7H1. This example shows a configuration in which a rectangular wave is obtained with a 1:1 ratio when the slope is upward, and a logic L when the slope is downward. The stage 401id for generating a reset pulse is formed by an inverter 609, OR gates 61L and 615, S-R flip-flops 613 and 614, an OR gate 615, and a single-wire multi-by-break 61G. 1 for the rectangular wave 702 output from the slope detection circuit 400;
The inverter 609 is connected to one input terminal of the OR gate 611 by i+fi. Further, the rectangular wave 702 is directly applied to one input terminal of the OR gate 612. The other input terminal of the OR gate 611 is supplied with a positive-phase rectangular wave signal 204 output from the control circuit 108 shown in FIG. The other input terminal of the OR gate 612 is connected to the control circuit 1.
08 is given as an inverse square wave signal 204. The outputs of OAG1-611 and 612 are the outputs of S-R flip-flops 613 and 614.
ni +6 t'ru. s -1 (Furi Ruff Flock 613
Reset the 1st pre-1 (Ni1) circuit ■02 (gives the negative phase rectangular wave A6-. Also resets the s-it off-flop 614 l' Q: #i child The control circuit 108 gives positive iu], li wave signals to the control circuit 108.
(The output signal of i 14 is given to the input voltage of the 7-leg multivibrator 01G after receiving the meacate 615, and is applied to the monostable multivibrator 616. , and in this pulse generator 402, it is added to the conventional reset valve 203 and applied to the gate means 112. It is as follows: From the slope 1 extraction bell) 400, 411.114 waves and -shi 702 are output as shown in Figure IP of Figure L5. This claw-shaped liquefaction +; 702 <71: The polarity is reversed by the inverter 609, and the rice is converted into No. 411 702 and supplied to the or gate 611. oagu ha11
A positive phase rectangular wave signal 204 output from the vg, I, fill I di, i means 108 is provided. Therefore, from the OR gate 611, the waveform Isa No. 50 shown in FIG.
1 is output. Square wave signals 702 and 204 are applied to OR gate 612 . Therefore, the small wave 502 shown in FIG. 5I is output from the OR gate 612.
3, and a positive-phase rp wave 204 is applied to the reset terminal of the s-i't frig-flock 613. The S-R flip-flop 613 is set when the rectangular wave 'IK number 501 applied to the set terminal S falls to the L logic, and the signal doctor applied to the reset terminal R is set when the signal doctor '7 is L.
It is reset when fiMi logic falls. Therefore S −
B, -5 from the output terminal Q of the R flip-flop 613
), a rectangular wave 503 is output. On the other hand, the set terminal SK of the S-R flip-flop 614
Since the rectangular wave signal 502 is applied and the positive phase rectangular wave signal 204 is applied to the reset terminal R, the S-R flip-flop 614 outputs the rectangular J high wave (i-i
- number 504 is output. S-R frill rough flop 61.3 Toro 14 The rectangular waves 503 and 504 that are outputted are converted to 1□615, and the r+'x shaped wave IB as shown in the fifth diagram is taken. The rectangular signal σ (signal 5 [ ] 5) output from the OR gate 615 is applied to the input terminal 1 of the monostable multi-noise break 616, and every time the coarse wave break 616 rises, Monostable multi-bi flake 616
is triggered, and outputs a node 506 shown in FIG. 5M from its output terminal Q. The final pulse 506 output from the monostable multivibrator 616 is a pulse obtained at the positive and negative peak points immediately after sampling. The pulse 50G is not output in the portion where the timing of surface sampling is the positive or negative peak point of the observed signal 2 (11) and in the portion where the peak is held.This pulse removal operation is performed by the inverter 609 and the OR gate. 611, 612, S R flip-flops 613, 614, OR gate 615, monostable multi-by-break 616 (off made to 1,
It is executed by the circuit. The pulse 506 is added to the original reset pulse 203 at the OR gate 402 to generate the pulse train signal 507.
and is supplied to the cage means 112. The gate means 112 generates a positive phase rectangular wave 204 and a negative phase rectangular wave 1
The pulse train signal 507 is divided into a reset pulse 508 for the positive peak hold circuit 103 shown in FIG. 5O and a reset pulse 509 for the negative peak hold circuit 104 shown in FIG. <Operations and Effects of the Invention> As explained above, according to the present invention, the reset pulse 506 is obtained at the positive and negative peak points of the observed signal 201 immediately after the sampling timing,
This reset pulse 506 is used as a reset pulse of the positive peak hold circuit 103 when the pulse obtained at the negative peak point is 14t, and the pulse obtained at the positive peak point is used to reset the negative peak hold circuit 104. By doing this, even if the voltage Ee in the middle of the dog-like peak waveform is held in the positive peak hold circuit 103 by the reset operation at time '■'4 shown in FIG. The reset pulse 506 is generated at the negative peak point 'I's' following , and this reset pulse 506 is applied to the positive peak bold circuit 103, so that the positive peak hold circuit 1 is activated at the time '1'4'.
The false hold 'abrasive pressure E6 held at 03 is reset to the negative peak voltage E8. Therefore, at this point 1゛4
′, the output voltage of the positive peak hold circuit 103 is applied =
tx Rise according to the slope of No. 118 No. 102, hold the positive peak value E9, and quickly rise to the next peak value E
Since the hold value is changed to lo, the peak value of the observed signal 201 can be accurately captured. Negative peak hold times at positive peak point 11!6
104, a peak signal that is largely biased toward the prefecture is input, and immediately after the peak signal that is largely biased in the negative direction, the
Even if the voltage is held, the negative peak hold circuit is reset at the next positive peak point, so false pressure will not be output to the sample hold circuit 106. Therefore, according to the present invention, the 91st measurement signal having a period shorter than the Zanning period is A-D converted and re-I)-A
If the present invention is applied to a spectrum analyzer that transforms the image and displays the analog output signal on a cathode ray tube, the false waveform 302 shown in FIG. 3 will not appear. Therefore, since the inconvenience of displaying erroneous measurement results can be eliminated, a highly reliable spectrum analyzer can be provided. Although the present invention has been described above as an example by comparing it to a spectrum analyzer, it is easily understood that the present invention can be applied to other devices that use A/D converters.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining the conventional peak detection device, Figures 2 and 3 are waveform diagrams for explaining the operation of the conventional peak 4 extraction device, and Figure 4 is the peak detection device according to the present invention. Block diagram for explaining the outline of the detection device, No. 5
The figure is a waveform diagram for explaining the operation of the mounting part of this invention.
f'j, Figure 6 is the 1l-Ij route of the expense department of this invention) ≦
5′]; Figure 7 explains the operation of the slope/f arrow circuit used in this invention.
It is a C-th waveform diagram. . 103, ILJ 4: Positive and 1j peak hold circuit, 105: Selection IIJ circuit, 106: Sample hold circuit, 108: fli! Ii1. l:1+
Means, 112: Kate means, 400 Nislov detection hand 1
Death, 401: Reset pulse 1, Raw means. Patent issued ML + entered Takeda Rikenko 81' removed from the ceremony"
-11j Takui Hitokusano 1 Hii 3 Figure O 2 Figure T

Claims (1)

[Claims] (1) A. Positive and negative peak hold circuits that hold the positive and negative peak values of the observed signal, and JS, a selection circuit that extracts the outputs of this pair of peak hold circuits from each other in conjunction with the sampling operation. and C0, a sample-and-hold circuit that extracts the hold pressure selected by this selection circuit at a constant cycle, D, a slope detection means for determining the rise and fall of the observed signal, and E, this slope construction means. Reset pulse generating means for generating a pulse for resetting the negative peak hold circuit at a positive peak point immediately after sampling and a pulse for resetting the positive peak hold circuit at a negative peak point immediately after sampling, based on the discrimination output. A peak detection device consisting of and.