JPS59214359A - Packet switching system - Google Patents

Abstract

PURPOSE:To facilitate the setting of circuit correspondence when a node processors connected to a host computer are changed by facilitating packet switching in a belonging node and between the belonging node and another node. CONSTITUTION:A packeted data input consisting of a node address part and an addressee host address part is transferred to a host computer specified by the addressee address of the packet; and a node processor transmits the packet through a common data bus, and the right to use the common bus and the right to use an addressee resource are transferred as a token through one control bus. This packet switching system sets node addresses in belonging nodes in each host computer and all node processors to ''0'', and each node processor performs switching processing so as to transfer a packet having a node address other than ''0'' transmitted from the belonging node to another node and a packet which is transferred from a different node and has its belonging node address into the belonging node while giving a node address ''0''.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention connects a plurality of host computers via a node processor and between the plurality of nodes, and the node processor transfers packets to a common data bus. The present invention relates to an improvement in a packet exchange method in which the right to use the common data bus and the right to use the other party's resource are exchanged through a looped control bus.

(2) Conventional technology and problems Conventional packet switching systems divide the data to be transmitted into small blocks, add the address of the destination to be sent, the address of the sender, etc. to some of the blocks, and treat them as one packet. Then, once the packet is taken into the computer by computer control, the destination address is determined and the packet is transferred to the nuclear output boat for packet exchange.Since this packet exchange method uses a computer, it takes a long time to exchange the packet. Large-scale hardware was required.

In response to this, in order to simplify the hardware of the exchange section and perform high-speed packet exchange, the present applicant filed a patent application filed in
No. 682.77 proposed a new packet switching method. In other words, in this method, packets are sent and received as tokens using the right to use a common data bus and the right to use the destination resource that guarantees that the packet will be accepted, through a control bus provided in a single loop. be. This enables high-speed packet exchange without requiring large-scale hardware and without causing contention for the common data bus and the receiving 1H buffer memory.

FIG. 1 shows an application of this proposed method to a communication system composed of a plurality of nodes. That is, all the groups of host calculations 111 to 11m, 121 to 121, etc. are exchanged and connected by the inter-node packet exchange unit 6 via the node processors t21+22, respectively. A unique pair of node address and host address is assigned to all of these host computers 111 to 11m+ 121 to 121, and the destination address section of the packet contains a node address corresponding to the host computer, regardless of whether it is within the own node or outside.

A host address pair is established for each node processor 21.
22 and other nodes, an exchange process based on the proposal is performed in the packet exchange unit 6.

In this case, a means is required to notify each host computer of its own node's address. As a means of doing so,
The node processor 21.22 notifies all the host computers 111 to 1x, l, , 121 to 121 in each node, or the host computers 111 to I1m are manually notified.
, 1z+ to 1+t using a keyboard or setting on a setting board in the computer.

゛Also, in all the line correspondence parts in the node processor 21122, in order to determine whether or not communication is within the own node,
It was necessary to set the own node address (NA) on a setting board, etc.

In the case of the conventional method, as the number of host computers increases or decreases, each time the node processors connected to these computers are changed, the host computer must be notified of the new node, and the I had to reconfigure the node address setting board in the line support section. As described above, there is a drawback in that it is troublesome to set the node processor to correspond to the line when changing the system connection.

(3) Purpose of the Invention The purpose of the present invention is to provide an entire packet switching system that simplifies the setting of line correspondence when changing the node processor connected to the host computer.

(4) Structure of the Invention In order to achieve the above object, the packet switching method of the present invention is a system in which a plurality of hosts are connected via a node processor, and the plurality of node processors are connected. A packetized data input consisting of a node address part and a destination host address part is transferred to the host computer indicating the destination address of the packet, and the packet is transmitted via a common data bus at the node 7° processor. In a packet exchange method in which the use of the common bus and the right to use the resources of the destination are exchanged as tokens through a single control bus, each host has its own node within 4M and all node processors. The address is controlled as "0", and the node processor transmits packets with a node address other than "0" sent from the own node to the node, and packets with the own node address transferred from other nodes are sent to the node. The feature is that the exchange process is performed so that the address is transferred within the own node as address "0".

(5) Embodiments of the invention Figures 2 and 6 are from the patent application filed by the proposing party in 1982-168277.
FIG. 2 is an explanatory diagram of the common bus and control loose signal formats, respectively, according to the data format of the No.

The data on the common bus in Figure 2 consists of the "flag", the destination node address (NA) and the destination host address (f(A
), the "data" preceded by the "destination address" are arranged, and the "check code (Fe2), J" is added at the end.

The control loose signal in FIG.
Vm, a token RVX indicating the usage of the receiving section resource of the interface section with other nodes, and a token DB indicating the right to use the common bus are arranged in this order.

The formats of these two signals are the same as in the proposed example, but the difference in the present invention is that the node address of the own node (
NA) is controlled as 11011, packets with a node address other than "D" sent from the own node (NA) are forwarded to other nodes, and packets with the own node address sent from other nodes with the own node address are transferred to the node. address"
0'' and transfer it within the own node.

By setting the own node address of the data to 0'' in this manner, exchange control between the own node and other nodes can be significantly simplified.

FIG. 4 is an explanatory diagram of the configuration of an embodiment of the present invention.

In the same figure, as shown corresponding to FIG. 1, host calculation +'A I 11 to 11□ is the node address (NA) in the data packet format of FIG. Let be 0''.

Further, when communicating with a host computer other than the own node, the node address (NA) 1 to n to which the other host computer belongs is set as the node address (NA). The data packet set in this way is sent to the node processor 21.

In the node processor 21, each host computer 111 to
1- corresponding channel corresponding parts 111 to 11□
An interface section (GWINF) 16 is provided for inputting and outputting these data packets through a common data bus and for exchanging packets with other node processors.

These channel correspondence units 111 to 11□ and the interface unit 16 have almost the same configuration, and the channel correspondence unit 1
11, the data packet shown in FIG. 2 sent from the host computer 111 is
It is recognized in the packet transmitter (PKTS) 21 +b of 11, and the sending buffer memo! , I (TBM). At the same time, the destination address (DA) of the data packet is the token control unit (TC) 23
1, and the resources of the channel correspondence unit corresponding to the destination host computer, such as the reception buffer memo of the packet reception unit (PKTR)! J (RBM) for ts m=t-identify the control-loose time slot for control passing.

The control loop includes each channel corresponding section 111 to 11.
□, Token in interface section 16 *lJ Gobe TC
25t to 26□, the time slot identification part of TC26 is connected in a loop, and the other party's receiver/1 is connected as shown in Fig. 6.
Token representing the right to renew the B-tributary source RV1 = RVN
, the looper 12 uses the time slot of the token RVx indicating the right to use the receiving section resources of the interface section with other nodes.
and is monitored by each token control unit (TC).

Send buffer memo in own node! , l (TBM)K When there is a data packet to be transferred, that is, in the case of NA-〇, according to the proposed example of rjiJ, the unused signal (RV(=
0), the corresponding RVi is in use (RV(=1
) and declare that the used laundry is occupied. In the case of NA~0, similar control is performed on the token RVx corresponding to the resource of the channel belonging to another node processor instead of the time slot corresponding to the HA.

Next, according to the proposed example, after waiting for the common data bus to become pending (I)B = 0), the DB is set to be in use (I)
DB=1) to declare the exclusive use right.

As a result, the transmission/reception switching unit (DV/, RV') 22
t, the data packets in the TBM of the packet transmitter (PKTS) are burst-transferred to the common data bus, and after the transmission is completed, the DB is released from occupation (DB=0).

If the above-mentioned packet data transmission is performed by another channel correspondence unit within the own node or a channel correspondence unit belonging to another node processor, the data packet is input to the transmission/reception switching m (DV/RV) 221 through the common data bus. ,
Captures data packets to be processed on its own channel.

That is, only packets in which the HA is the own host address at NA-0 are received by the packet receiving unit (PKTR) 21la, and buffered in the reception buffer memo') (RBM). Next, the packet is transferred to the destination host computer, and the RBM becomes empty, making the RV (of the time slot corresponding to its own channel unused (f%V<
-0) to release the usage right.

Next, the packet receiving unit (GPKTR) in the interface unit (GWINF) 15 24. Then from the common bus D
Of the data input throughout the V/RV 25, only packets NA to 0 are stored in the reception buffer memory (RB, fi'
) 1 and sent to Kazuya's node gross length.

In addition, the packet transmitter (GPK
In TS) 24b, the packet from the other node's processor to the own node is stored in the transmission buffer memory (Tf3M).
After buffering as A=0 and setting NA=0 for the token control unit (TC) 26, DV/RV2
5, data packets are sent to the own node processor.

,;g Figures 5 and 6 are detailed explanatory diagrams of the main parts of the embodiment shown in Figure 4, respectively.

FIG. 5 shows a control circuit for controlling the own node address of packet data for the packet transmitter.

In the same figure, there is a buffer memo for sending data from the host computer. , I(TBM), and also temporarily stores it in the transmission address register 60 in the token control unit (T(1) 23, and sends the node address (NA) to the 0 judgment circuit 31. If it is 0 as described above, Within own node,
If it is 1 to n, it is determined that it is within another node, and based on this determination signal, either the host address (HA) of the address register 60 input to the selector 66 or the host address X of the channel corresponding section of the other node is selected and output. . This output is input to the matching circuit 34, and the control loose time slot is input to the synchronization circuit 6 to obtain the timing of the destination token.
5 to the time slot counter 36 to obtain a match signal between the address number of RVI to RVw or RVx output from the selector 66 and the time slot count number, and send it to the judgment/insertion circuit 38 controlled by the synchronization signal. Input,
Furthermore, by decoding the count value of the time slot counter 36 with the decoder 67 and inputting the timing of the common data bus token DB to the determination/insertion circuit 68, the RVj and DB tokens corresponding to the destination host of the control loose are determined. Control. Based on the result, a transmission enable signal is output from the TC23 and the transmission/reception unit (DV/R
V) Control 22.

FIG. 6 shows a 'NU control circuit for the own node address of packet data from the common data bus for the packet receiving section.

In the same figure, packet data from other nodes is received by f) VAV 22 through a common data bus, and a reception buffer memo! j (R43M) and the token control unit (TC) 23, and the destination host address (f (AL sono-address (NAL flag (F)) is sent to the shift register 40.
) Temporarily store money. This flag indicates input from the common data bus, and the outputs of the flag determination circuit 44 and the node address (NA) 0 determination circuit 46 are combined into an AND circuit 45.
The passed output is input as an enable signal to the matching circuit 42, and the address signal from the own host address 41 and the address signal of n light amount from the host address (f(A)) in the shift register 40 are input to this matching circuit 42. When a matching signal is obtained, the gate 46'e opens and the corresponding node data is sent to the receiving buffer memory!J (RBM).
Store in.

As shown in FIGS. 5 and 6 above, by setting the own node address to OH, the 0 determination circuit 6 in FIG.
1 and the selector 66, in FIG.
Flag determination circuit 44. By using the AND circuit 45 and the matching circuit 42, it is possible to simplify t4 the node transformation from p1's own node to other nodes and from other nodes to its own node.

(6) As described in detail, according to the present invention, the node address of the own node is controlled as "0" in each host calculation table and in all node processors, and the node address of the own node is controlled as "0". Packets with node addresses other than ``'0'' are forwarded to other nodes, and packets sent from other nodes in the first class and having their own node address μ node address ``0''
The exchange process is performed so that the data is transferred within the local node as a. This greatly simplifies packet conversion within the own node and between the own node and other nodes, and when changing the node grosser, there is no need for hardware configuration such as setting up an address setting board in each line corresponding section. Therefore, simply changing the software is sufficient.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a packet switching communication system to which the present invention is applied, FIGS. 2 and 3 are explanatory diagrams of the packet data format of the present invention, and FIG. 5 and 6 are detailed explanatory diagrams of the main parts of the embodiment shown in FIG.
11m is a channel corresponding section, 12 is a looper, 16 is an interface section, 211 (L + 21 ma r248 is a packet transmitting section, 211b, 21mb, 24b is a packet receiving section, 22r + 22m, 25 is a transmission/reception switching section, 2
31+23m+26 indicates a token control unit. Patent applicant: Sub-agent of Shitsu Co., Ltd. Patent attorney 1) Yoshitaka Saka

Claims (1)

[Claims] multiple host computations) through node processors,
and a plurality of node processors connected thereto, a packetized data input consisting of a node address field and a destination host address field is transferred to the host computer indicating the destination address of the packet, and the node processor In this system, packets are transmitted via a common data bus, and packets are exchanged using a single control bus as the right to use the common bus and a token for use of the other party's resources at the destination. All node processors control their own node's node address as 0'', and the node processor transfers packets with node addresses other than 0 that are sent from its own node to other nodes, and from other nodes sends them to +. A packet switching method characterized in that a packet having a self-node address among the received packets is exchanged so as to be transferred within the self-node as a node address "0".