JPS5921230B2 - PLL synthesizer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL synthesizer device used for channel setting in devices having a large number of channels, such as transceivers.

When the number of channels increases in a transceiver or the like (23CH to 50CH), it is common to add a PLL synthesizer device to expand the transmission and reception frequency range.

Known PLL synthesizer devices used for such purposes use programmable counters (down counters) and rotary or Samir switches for channel setting.

For example, if we take a PLL synthesizer device used in a transceiver having a large number of channels, 23CH to 50CH, its programmable counter is 6 to 7.
It is composed of flip-flops (hereinafter referred to as FF),
A numerical value corresponding to the number of channels was set in this programmable counter in binary notation.

However, in such a PLL synthesizer device, a rotary switch or a Samir switch with a special mechanism must be used to set the number of channels, which increases the cost of the device. In order to achieve this, external lead-out terminals corresponding to the number of FFs used are required, which increases the number of terminals on the integrated circuit and increases the cost of the integrated circuit. In this case, it is necessary to secure space to store these items, and the equipment becomes larger.Also, regardless of which switch is used, the channel setting is done by rotating the switch, which makes it difficult to set the channel. There were various problems such as time consuming.

The present invention was made to eliminate the disadvantages that existed in such known PLL synthesizer devices, and the number of channels is set by a variable resistor in a pulse expansion circuit consisting of one D-type flip-flop (hereinafter referred to as DFF). The present invention provides a PLL synthesizer device that can perform the following steps.

The PL'L synthesizer device of the present invention will be described in detail below with reference to the drawings.

As shown in the block diagram of FIG. 1, the PLL synthesizer device of the present invention includes a reference frequency oscillation circuit 1, a frequency dividing circuit 2,
Phase comparison circuit 3, low-pass filter circuit 4, voltage controlled oscillation circuit 5
, a local oscillation circuit 6, a frequency mixing circuit 7, and a DFF 8 as main components, and a pulse stretching circuit 1 consisting of a resistor 9, a capacitor 10, a variable resistor 11, and a transistor 12.
3, a counter 14, a latch circuit 15, a decoder 16, and a display 17.

Note that 18 is an output terminal.

In the PLL synthesizer device of the present invention having the above configuration, it is assumed that a signal of frequency fs is output from the reference frequency oscillation circuit 1, and this signal is frequency-divided by the frequency dividing circuit 2.

If the number of division stages of this frequency dividing circuit is p, the frequency of the output signal of the frequency dividing circuit 2 (synthesizer frequency) is f s /
2 It is hailed by P.

This output signal is applied to the phase comparison circuit 3 as one input.

On the other hand, the signal with the frequency fo output to the output terminal 18 and the signal with the frequency fL output from the local oscillation circuit 6 are mixed in the frequency mixing circuit 7, and the second signal with the frequency fo-fL is mixed from the frequency mixing circuit 7. A signal shown in FIG. A is output and applied to the trigger terminal T (hereinafter referred to as T terminal) of the DFF 8 which is the main component of the pulse expansion circuit 13.

When such a signal is applied, the potential of the output terminal D (hereinafter referred to as "terminal") of the DFF 8 is the same as that of the capacitor 10.
is charged by the power supply voltage vcc through the resistor 9 and the variable resistor 11, and gradually rises as shown in FIG. , Therefore, the output terminal Q (hereinafter referred to as Q terminal) becomes "L"'.

If the transistor 12 connected to the Q terminal is an N-channel enhancement type MOS transistor, the transistor 12 is cut off under this situation.

However, as the charging of the capacitor 10 progresses and the potential at the D terminal exceeds the threshold voltage ■·F and reaches a high level (hereinafter referred to as T+ H11), the frequency applied to the T terminal as shown in FIG. 2A, f O- At time t1 when the level of the fL signal becomes L', the DFF8 is inverted, the level of the Q terminal becomes 'H', and transistors 1 to 12 become conductive.

Further, the charge accumulated in the capacitor 10 is rapidly discharged through the resistor 9 and the transistor 12 from time t1 when the transistor 12 becomes conductive.

In the transistor 12, the D terminal becomes 'L' due to the discharge of the charge of the capacitor 10, and after this, the level of the signal applied to the T terminal becomes 'L'. In order to maintain the conductive state until time +2, the discharge of the capacitor 10 continues for a period of τ1 from tl to +2.

Note that at time t2, the transistor 12 is cut off, so the charging path for the capacitor 10 is formed again, the capacitor 10 is charged, and the Q terminal is inverted to H'' at +3.
The operation of returning to L'' at +4 is repeated.

FIG. 2C shows the output pulse waveform of the Q terminal whose level changes due to the above operation.

By the way, the value of the resistor 9 is R9, the capacitance of the capacitor 10 is C1o, the sum voltage of the transistor 12 is Vsat, and the time width from tl to +2 is τ (one cycle of the signal whose frequency is fO-fL applied to the T terminal). ), the terminal voltage (highest potential) of the capacitor 10 at the time of tl and +2゛ is 1, and the terminal voltage (lowest potential) of the capacitor 10 at the time of +2 and +4 is v2, then the voltage of the capacitor 10 is The difference ■, -v2 is calculated by the following formula.

Furthermore, the time τ2 from +2 to 13 changes the power supply voltage to vc
If the value of the c variable resistor 11 is R11, it is expressed by the following equation.

■cc-■2',=C1o('%"""""(V(30-V2)-(
VI -'7''-' (2) When equation (1) is substituted into equation (2), equation (2) is rewritten as follows.

The time width τ2 from t2 to t13 of the output pulse signal output to the Q terminal of the DFF8 shown in FIG.
As is clear from the equation, the output pulse signal outputted to the Q terminal can be controlled by the value Ra1 of the variable resistor 11, and the pulse signal applied to the T terminal shown in FIG. 2A (frequency fo -fr, ).

Note that the frequency of the output pulse signal of the Q terminal is the number of pulses of the pulse signal of the frequency fo−fL applied to the T terminal that exists within the time width (τ1 + τ2) corresponding to one cycle of this pulse signal. If N, (fo fL)/N
Hail as.

The output pulse signal of the Q terminal expressed in this way, that is, the output pulse signal of the pulse expansion circuit 13, is applied to the phase comparator circuit 3 as the other input.

In the phase comparator circuit 3, the output pulse signal of the frequency dividing circuit 2 having a frequency of fs/2p and the output pulse signal having a frequency of (f.

-fL)/N is compared with the output pulse signal of the pulse expansion circuit 13, and if the frequencies of both signals are different, a predetermined signal is output from the low-pass filter circuit 4 connected to the phase comparison circuit 3. A voltage higher or lower than the voltage is output.

The voltage controlled oscillation circuit 5 has an oscillation frequency f depending on the output voltage (DC voltage) of the low-pass filter circuit 4.

A pulse signal of this oscillation frequency fo is output from the output terminal 18.

By the way, the phase comparison circuit 3, the low-pass filter 4, the voltage controlled oscillation circuit 5, the frequency mixing circuit 7, and the pulse expansion circuit 13
forms a closed loop, so this closed loop is composed of the frequency f S/2 of the signal output from the frequency dividing circuit 2 and the frequency (f, -fL) of the output pulse signal of the pulse expansion circuit 13.
)/N, and therefore the following equation holds true.

'°'・-'・ ...... (4) p N From equation (4), the frequency fo of the signal output to the output terminal 18 is 5 fo = fL + N"""" (5) As p Hail.

In other words, the output frequency f is determined by the number of pulses N.

is frequency synthesized.

Note that the number of pulses N is controlled by the time width τ2 shown in equation (3), and τ2 is controlled by the value R11 of the variable resistor 11. Therefore, the number of channels can be set by the variable resistor 11. can.

The display 17 is for displaying the set number of channels, and in order to display the number of channels on this display 1γ,
After resetting the counter 14 with the signal shown in the second diagram, the signal output from the frequency mixing circuit 7 [FIG. 2 A] is counted, and this counted value is stored in the latch circuit 15 as the signal shown in FIG. 2 E. and the contents of the latch circuit 15 are sent to the decoder 16.
The information may be sent to the display 17 via the .

As explained above, the PLL synthesizer device according to the present invention allows the number of channels to be set by changing the value of the variable resistor in the pulse expansion circuit mainly composed of the DFF. It is no longer necessary to use a programmable counter (consisting of several FFs) and rotary switches or Samir switches as in conventional devices, so when converting the device into an integrated circuit, the external lead-out terminals corresponding to the number of FFs used are No need,
Costs can be reduced, and there is no need to secure space for accommodating each switch, making it possible to downsize the device.

Furthermore, since the channel can be set simply by changing the value of the variable resistor, the channel setting can be completed in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a PLL synthesizer device according to the present invention, and FIGS. 2A to 2E are timing charts showing waveforms of essential parts to explain the operation of the device. 1... Reference frequency oscillation circuit, 2... Frequency dividing circuit, 3... Phase comparison circuit, 4...
Low-pass filter circuit, 5... Voltage controlled oscillation circuit, 6.
... Local oscillation circuit, 1 ... Frequency mixing circuit, 8 ... D-flip-flop, 9 ...
...Resistance, 10...Capacitor, 11...
...Variable resistor for setting the number of channels, 12...
Transistor, 13...Pulse extension circuit, 14
...Counter, 15...Latch circuit,
16... Decoder, 17... Display unit,
18...Output terminal.

Claims (1)

[Claims] 1 D-type flip-flop, a capacitor connected between the D terminal of the flip-flop and the ground point, a variable resistor connected between the above terminal and the power supply terminal, and a switch operation based on the output level of the D flip-flop. a transistor for opening and closing a discharge path of the capacitor; a pulse extension circuit for extending a pulse signal applied to a trigger terminal of the flip-flop by charging and discharging the capacitor; and an output of the pulse extension circuit. a phase comparison circuit that compares the phases of the signal and the output signal of the reference frequency oscillation circuit; a low-pass filter circuit whose output voltage level is controlled by the output signal of the phase comparison circuit; and an output voltage of the low-pass filter circuit. a voltage-controlled oscillation circuit whose oscillation frequency is controlled by the voltage-controlled oscillation circuit, and subtracts the frequency of the output signal of the local oscillation circuit from the frequency of the output signal of the voltage-controlled oscillation circuit, and the bird applies a signal with the difference in frequency to the terminal. and a frequency mixing circuit that generates a pulse signal, and the number of channels is set by controlling the charging time of the capacitor with a variable resistor connected between a power supply terminal and the above terminal. PLL synthesizer device.