JPS59212010A - Gata quantizing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a data quantization device.

In the prior art, a quantizer determines whether a received digital signal is above or below a predetermined threshold level. Typically, a comparator circuit comprising an emitter-coupled transistor pair is used as a quantizer. delay flip
Such quantizers connected in tandem with flops are used as decision circuits in digital transmission systems. A delay flip-flop requires the amplitude of its input signal to be above a predetermined threshold level in order to produce an 11. output. The flip-flop also requires the input signal amplitude to be below another threshold level in order to produce a %01 output. The difference between the two threshold levels is called dynamic sensitivity.

A comparator, typically comprising an emitter-coupled transistor pair, is used as a quantizer to provide an input signal to a delay flip-flop.

When such quantizers are typically used with delay flip-flops, the gain of the quantizer is so small that the dynamic sensitivity cannot be reduced to an acceptable level. The gains of such circuits of the prior art are typically in the 10-20 range.

In accordance with the present invention, a data quantizer includes a first pair of emitter-coupled transistors biased in the non-saturation region of its operating characteristics to produce a quantized output signal in response to an input signal; biased into the saturation region,
A second pair of emitter-coupled transistors is responsive to the quantized output signal to generate an enhanced quantized output signal.

The monolithically integrated data quantization circuit includes a plurality of cascaded emitter-coupled transistor pairs. Each pair uses transistors of the same conductivity type. Transistors of opposite conductivity types are used in adjacent pairs. The gain is much higher than prior art quantizers and therefore provides excellent amplitude discrimination.

The present invention will be explained below with reference to the accompanying drawings.

Referring to FIG. 1, a data quantization circuit 10 is shown. The quantizer circuit includes two pairs of emitter-coupled bipolar transistors. The NPN transistor input pair 12 and 13 are interconnected by a conductor between their emitters. A common emitter circuit resistor 15 interconnects a conductor between the emitters of transistors 12 and 13 and a negative polarity bias voltage source 14. Resistor 15 and bias source 14 cause a constant emitter current to flow through resistor 15.

Determine the value of

Base input resistors 18 and 19 are connected between the base electrodes of transistors 12 and 13, respectively, and ground 20. Resistors 18 and 19 are connected to transistors 12 and 1
3 provides a path for base bias current and provides a resistive input termination.

Two input signals are applied to circuit 10 in a balanced manner. The input signal swings the positive and negative electrodes with respect to the quiescent voltage. When the two input signals are applied in equilibrium, one input is connected to terminal 22 of the base electrode of transistor 12. Complementary input is transistor 13
is connected to the terminal 23 of the base electrode.

Alternatively, the input signal can be applied to circuit 10 in a single-ended manner.

For example, if a single-ended input signal is applied to terminal 22, terminal 23 will be in a floating state.

A series of diodes 21 and a pair of load devices, such as resistors 25 and 26, connect the positive collector bias voltage source 2
8 and the collector electrodes of the respective transistors 12 and 13.

The voltages of voltage sources 14 and 28 and the values of resistors 15, 25 and 26 are chosen to ensure that transistors 12 and 13 never operate in saturation. By avoiding saturation, high operating speeds are possible.

It is also necessary that the amplitude of the output signal from the input transistor pair 12 and 13 be less than or equal to the breakdown voltage of the output transistor pair described below.

In operation, one of transistors 12 and 13 is biased to become more conductive and the other becomes more non-conductive in response to an applied input signal. This operation can be expressed by the following equation.

■.

However, here II2 is the current flowing through the transistor 12, v,
! -ts is the input signal voltage between terminals 22 and 23 with respect to terminal 22, q is the electron charge, k is Portzmann's constant, and T is the absolute temperature.

A similar equation holds true for transistor 13 as well.

When a positive input signal is applied to the input terminal 22 and its complementary signal is applied to the input terminal 23, the transistor 12
becomes more conductive, and transistor 13 becomes more non-conductive.

Electrician.

flows through the collector-emitter path of transistor 12. Less than half of the current I is in transistor 1
Flows through the collector-emitter of 3.

Referring to FIG. 2, there is shown an operating characteristic curve 24 for an input signal voltage 30 applied between input terminals 23 and 22 with respect to terminal 23 as shown in parentheses along the horizontal axis.

An output signal voltage 31 is generated between terminals 32 and 33 with respect to terminal 32 as shown in parentheses along the vertical axis. Output signal 31 is an amplified version of input signal 30.

The operating characteristic curve 24 is mathematically expressed by the following equation.

(2) VS2-1 here! l is the output signal between nodes 32 and 33 with node 32 as the reference, and V23-22
is the input signal voltage between input terminals 22 and 230 with respect to terminal 23, RL, = R2L+, = R
. The gain is represented by the slope of curve 24 and is typically in the range of 10-20 for small signals.

As seen in the output signal 31, since the signal amplitude is limited, amplitude discrimination is almost impossible. What is amplitude discrimination?2
Refers to the process of generating an output signal whose amplitude is a function of the relative amplitudes of two input signals.

The two PNPt transistors 42 and 43 are interconnected at their emitters. A common emitter resistor 45 is connected between voltage source 28 and the emitters of transistors 42 and 43. Resistor 45 and bias source 28 determine the value of the constant emitter current I2 flowing through resistor 45.

Output signals, such as signal 31, generated between nodes 32 and 33 from input pair transistors 12 and 13 are applied directly to the base input electrodes of transistors 42 and 43, respectively.

Load devices such as resistors 48 and 49 are connected to transistor 42.
and 43 and the ground air 20, respectively.

The voltage of voltage source 28 and the values of resistors 25, 26, 45, 48 and 49 are selected to ensure that transistors 42 and 43 operate without saturation. By operating transistors 42 and 43 in this region,
Since the transistor does not saturate, it can operate extremely fast. The magnitude of the output voltage is less than or equal to the breakdown voltage of the subsequent device.

During operation, in response to a signal between nodes 32 and 33,
One of the transistors 42 and 43 is biased so that more than half of the current 2 flows, and the other is biased so that less than half of the current 2 flows. In accordance with the previous example, the signal amplitude between nodes 32 and 33 quickly causes transistors 42 and 43 to enter a nonlinear operating state.

As shown in FIG. 3, the operating characteristic curve 50 of transistors 42 and 43 is nonlinear.

The input signal 37 to the output transistor pair is the signal between nodes 33 and 32 with respect to terminal 33 as shown in parentheses along the horizontal axis.

As shown in FIG. 3, a quantized output voltage signal 51 appears at output terminals 52 and 53 of the circuit of FIG. Here, output terminals 52 and 53 are connected to the collectors of transistors 42 and 43, respectively. A substantially quantized voltage waveform 51 appears between output terminals 52 and 53. This voltage is referenced to terminal 52 as shown in parentheses along the vertical axis.

The operating characteristic curve 50 is expressed by the following equation.

VS2-53-RL・'(1vss-32°9/kT
)(3)l+e Here, VS2-43 is the output terminal 5 with the terminal 52 as the reference.
The output signal voltage is between 2 and 53, and V33-31! is the input signal voltage between nodes 32 and 33 with respect to node 33, and RL2-R48,=R40.

Operating characteristic curve 50 of FIG. 3 represents the operating characteristic curve of a single output stage of the circuit of FIG.

Gain is represented by the slope of curve 50.

Since the signal appearing between nodes 33 and 32 is an amplified version of input signal 30 applied between terminals 23 and 22, output signal 51 is enhanced by being quantized.

The fast rise time and large amplitude of the output signal 51 ensure excellent amplitude discrimination ability and rapid passage through the dynamic sensitivity range between the thresholds of the delay flip-flops connected in response to the signal.

As shown in FIG. 4, the operating characteristics 54 of the quantizer 10 including two stages, ie, a plurality of emitter-coupled transistor pairs (see FIG. 1), are the operating characteristics 55 of a single-stage quantizer used in the prior art. It is compared with. The gain of a two-stage quantizer is a dog above the gain of a prior art single-stage quantizer. As a result of the operation of the two-stage quantizer, better amplitude discrimination occurs and faster rise time output pulses are obtained at output terminals 52 and 53. These enhanced output pulses improve the operating speed and performance of a decision circuit using a two-stage quantizer compared to a single-stage quantizer.

Input limiter coupling pair transistors 12 and 13 are NP
Since the output capacitor coupling pair transistors 42 and 43 are PNP transistors,
There is no need for level shifting between these emitter pairs. Operating speeds are maintained at high speeds by avoiding such level shifts.

It is advantageous if the quantization device 10 is manufactured as an integrated circuit. Processes for manufacturing transistors of opposite conductivity type as monolithic integrated circuits capable of operating at frequencies in the microwave frequency range are well known. One process that can be used to form circuits is W.E. Beadle (W,
E, Beadle), Niss F. Moya (S.
, F. Moyer) and Ni-Ni Yiannoulos (N. A., Yiannoulos).
dComplementary Vertical T
The now abandoned 1
No. 658,586, filed Feb. 17, 976. Other processes that may be used to form the circuit include slight modifications of the processes described above. This modified process
No. 337,707, filed January 7, 1982, by D.G. Roas.

[Brief explanation of the drawing]

Figure 1 is a style diagram of the quantization circuit, Figure 2 is the input/output response characteristic of the single-manual stage of the circuit in Figure 1, and Figure 3 is the input/output response characteristic of the output stage of the circuit in Figure 1. FIG. 4 is a diagram showing a comparison of operating characteristic curves of the two-stage quantization circuit shown in FIG. 1 and the single-stage quantization circuit. [Explanation of symbols of main parts] Claims Code Code data quantization device 10 First emitter-coupled transistor pair 12.13 Second emitter-coupled transistor pair 42.43 (15) Feather 53-

Claims (1)

[Claims] 1. A first device whose operating characteristics are biased into the non-saturation region and which generates a quantized output signal in response to an input signal.
a second emitter-coupled transistor pair whose operating characteristics are biased into the non-saturation region and responsive to the quantized output signal to generate an enhanced quantized output signal.
A data quantization device comprising: a pair of emitter-coupled transistors. 2. In the quantization device according to claim 1,
A quantization device characterized in that the first pair of transistors has a first conductivity type and the second pair of transistors has a second conductivity type. 3. A quantizer according to claim 2, wherein the first pair of transistors is directly interconnected with the second pair of transistors by providing a level shifting circuit. 4. The quantization device according to any one of claims 1 to 3, wherein the first and second transistor pairs are bipolar transistors. 5. A quantization device according to any one of claims 1 to 4, characterized in that the first and second transistor pairs are manufactured as a monolithic integrated circuit. 6. In the quantization device according to any one of claims 1 to 5, the first and second transistor pairs are made to operate at a frequency in the microwave frequency range. Characteristic quantization device. 7. The quantization device according to any one of claims 1 to 6, wherein the output signal has an extremely high gain.