GB2139837A - Improvements in or relating to data quantizers - Google Patents

Abstract

A monolithic integrated circuit data quantizer (10) includes plural cascaded emitter-coupled pairs of transistors. Each pair (12,13; 42,43) uses like conductivity transistors. Opposite conductivity types of transistors are used in adjacent pairs. Gain is very high enabling excellent amplitude discrimination. No level shifting is required between the adjacent pairs of opposite conductivity types of transistors. <IMAGE>

Description

SPECIFICATION Improvements in or relating to data quantizers This invention relates to data quantizers.

In the prior art a quantizer circuit determines whether a received digital signal is above or below a predetermined threshold level. Typically a comparator circuit including an emitter-coupled pair of transistors is used for a quantizer. Such a quantizer, in tandem with a delay flip-flop is used in a digital transmission system as a decision circuit. The delay flip-flop requires the magnitude of its input signal to be above a predetermined threshold level to produce a "one" output. It also requires the magnitude of the input signal to be below another threshold level to produce a "zero" output. The difference between these two threshold levels is called dynamic sensitivity.

Typically a comparator including an emitter-coupled pair of transistors is used as a quantizer for supplying input signals to the delay flip-flop. When such a quantizer is used with a typical delay flip-flop, the gain of the quantizer is too low to reduce the dynamic sensitivity to an acceptable level. Gain in such prior art circuits typically is in a range of 10-20.

According to this invention a data quantizer includes a first emitter-coupled pair of transistors biased in a nonsaturated region of their operating characteristic and responsive to an input signal for producing a quantized output signal, and a second emitter-coupled pair of transistors biased in a nonsaturated region of their operating characteristic and responsive to the quantized output signal for producing an enhanced quantized output signal.

A monolithic integrated data quantizer circuit may include plural cascaded emitter-coupled pairs of transistors. Each pair uses like conductivity transistors. Opposite conductivity types of transistors are used in adjacent pairs. Gain is an order of magnitude higher than the prior art quantizer thus enabling excellent amplitude discrimination.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a quantizer circuit; Figure 2 shows an input-to-output response characteristic for a single input stage of the circuit of Figure 1; Figure 3 shows an input-to-output response characteristic for an output stage of the circuit of Figure 1; and Figure 4shows a comparison between an operating characteristic curve for the two-stage quantizer circuit of Figure 1 and a single-stage quantizer circuit.

Referring now to Figure 1,there is shown a data quantizer circuit 10. The quantizer circuit includes two emitter-coupled pairs of bipolar transistors. An input pair of NPN transistors 12 and 13 is interconnected by a lead between their emitter electrodes. A common emitter circuit resistor 15 is connected from the lead between the emitters of the transistors 12 and 13 to a source 14 of negative polarity bias voltage. The resistor 15 and the bias source 14 determine a constant value of emitter current 11 that is conducted through the resistor 15.

Base input resistors 18 and 19 are connected between the respective base electrodes of the transistors 12 and 13 and ground potential 20. Resistors 18 and 19 provide a path to conduct base bias currentforthe transistors 12 and 13 and also provide a resistive input termination.

Input signals can be applied balanced to the circuit 10. The input signals make positive and negative polarity swings with respect to a quiescent potential. When input signals are applied balanced, one input is connected to a terminal 22 at the base electrode of the transistor 12. The complementary input is connected to a terminal 23 at the base electrode of the transistor 13.

Alternatively an input sig nal can be applied single-ended to the circuit 10. If for example the single-ended input signal is applied to the terminal 22, the terminal 23 is left floating.

A series of diodes 21 and a pair of load devices, for example, resistors 25 and 26 are connected between a source 28 of positive polarity collector bias potential and the collector electrodes of the respective transistors 12 and 13.

The potential of the sources 14 and 28 and the values of the resistors 15,25 and 26 are selected to ensure that the transistors 12 and 13 never operate in saturation. By avoiding saturation, a high operating speed is possible. Also it is important that the magnitude of the output signal from the input pair of transistors 12 and 13 is below the breakdown voltage of an output pair of transistors, to be described.

During operation, one of the transistors 12 and 13 is biased to conduct more while the other conducts less in response to an applied input signal. Such operation can be represented by an expression

wherein 112 iS the current conducted by the transistor 12, V22-23 is the input signal voltage between the terminals 22 and 23 with terminal 22 as a reference, q = the charge on an electron, K = Boltzman's constant, and T = temperature in degrees Kelvin.

A similar expression applies to the transistor 13.

When a positive polarity input signal is applied to the input terminal 22 and its complementary signal is applied to the input terminal 23, the transistor 12 conducts more. The transistor 13 conducts less. More than half of the current Ii is conducted through the collector-to-emitter path of the transistor 12. Less than half of the current Ii is conducted through the collector-to-emitter of the transistor 13.

Referring now to Figure 2, there is shown an operating characteristic curve 24 for an input signal voltage 30 applied between the input terminals 23 and 22, with terminal 23 as a reference as shown in the brackets along the horizontal axis. Output signal voltage 31 is produced between the terminals 32 and 33, with terminal 32 as a reference as shown in the brackets along the vertical axis. The output signal 31 is an amplified version of the input signal 30.

The operating characteristic curve 24 can-be shown mathematically by an expression

wherein V32-22 is the output signal voltage between nodes 32 and 33 with node 32 as a reference, V23-22 is the input signal voltage between the input terminals 22 and 23 with terminal 23 as a reference, and RL1 = R25 = R269 Operating characteristic 24 of Figure 2 is representative of both the single input stage of the circuit of Figure 1 and the prior art quantizer circuit for small signals of interest. Gain is represented by the slope of the curve 24 and typically is in a range of 10-20forthe small signals. As shown by the output signal 31, little amplitude discrimination is possible because of the limited signal amplitude.Amplitude discrimination is a process of producing an output signal having an amplitude that is a function of the relative magnitudes of two input signals.

Two PNP transistors 42 and 43 are interconnected at their emitters. A common emitter resistor 45 is connected between the source 28 and the emitters of the transistors 42 and 43. The resistor 45 and the bias source 28 determine a constant value of emitter current 12 that is conducted through the resistor 45.

Output signals, such as the signal 31,from the input pair of transistors 12 and 13, and produced between the nodes 32 and 33, are applied directly to the base input electrodes of the transistors 42 and 43, respectively.

Load devices, such as resistors 48 and 49, are connected, respectively, between the collectors of the transistors 42 and 43 and the ground potential 20.

The potential of the source 28 and the values of resistors 25,26,45,48 and 49 are selected to ensure operation of the transistors 42 and 43 without saturation. By operating them in this region, the transistors can operate very fast because they do not go into saturation. The magnitude of the output voltage is less than the breakdown voltage of the subsequent device.

During operation and in response to the signal between the nodes 32 and 33, one of the transistors 42 and 43 is biased to conduct more than half the current 12 while the other conducts less than half. In accordance with the aforementioned example and because of the magnitude of the signal between the nodes 32 and 33, the transistors 42 and 43 rapidly are driven into nonlinear operation.

As shown in Figure 3, the operating characteristic curve 50 for the transistors 42 and 43 is nonlinear. The input signal 37 to the output pair of transistors is the signal between the nodes 33 and 32, with terminal 33 as a reference as shown in the brackets along the horizontal axis.

As shown in Figure 3, a quantized output voltage signal 51 occurs in the circuit of Figure 1 at output terminals 52 and 53 which are connected, respectively, with the collectors of the transistors 42 and 43. A substantially quantized voltage waveform 51 appears between the output terminals 52 and 53. It is referenced to terminal 52 as shown in the brackets along the vertical axis Operating characteristic curve 50 can be represented by an expression

wherein V52-53 is the output signal voltage between the output terminals 52 and 53 with terminal 52 as a reference, V33-32 is the input signal voltage between the nodes 32 and 33 with node 33 as a reference, and RL2 = R48 = R49.

Operating characteristic curve 50 of Figure 3 is representative of the single output stage of the circuit of Figure 1. Gain is represented by the slope of the curve 50.

Because the signal appearing between the nodes 33 and 32 is a substantially amplified version of the input signal 30 applied between the terminals 23 and 22, the output signal 51 is enhanced by being substantially quantized. The fast rise time and the large amplitude of the output signal 51 ensure excellent amplitude discrimination and very rapid traverses of the dynamic sensitivity region between thresholds of any delay flip-flop that is connected to be responsive to this signal.

As shown in Figure 4, the operating characteristic 54 of the quantizer 10 including the two stages, or pairs of emitter-coupled transistors, as shown in Figure 1, is compared with the operating characteristic 55 of a single stage quantizer as used in the prior art. Gain of the two stage quantizer is an order of magnitude greater than the gain of the single stage quantizer of the prior art. As a result of the two stage quantizer operation, better amplitude discrimination occurs and a faster rise time output pulse is available at the output terminals 52 and 53. These enhanced output pulses significantly improve the speed and quality of operation of a decision circuit using the two stage quantizer over the operation of a single stage quantizer.

Because the input emitter coupled pair of transistors 12 and 13 are NPN transistors and the output emitter coupled pair of transistors 42 and 43 are PNP transistors, any need for level shifting between the pairs is eliminated. Speed of operation is maintained at a high rate by avoiding such level shifting.

It is advantageous to fabricate the quantizer 10 as an integrated circuit. There are known processes for fabricating the opposite conductivity type transistors as a monolithic integrated circuit capable of operating at frequencies as high as the microwave frequency range. One process which can be used for making the circuit is a process described in a now abandoned U.S. patent application, Serial No. 658,586, filed on February 17, 1976 in the names of W. E. Beadle, S. F. Moyer and A. A. Yiannoulos and entitled "Integrated Complementary Vertical Transistors". Another process which can be used for making the circuit is a slighty modified version of the just mentioned process. Such modified version is described in a U.S. patent application, Serial No.337,707, filed January 7, 1982 in the name of D. G. Ross.

Claims (8)

1. A data quantizer including a first emitter-coupled pair of transistors biased in a nonsaturated region of their operating characteristic and responsive to an input signal for producing a quantized output signal, and a second emitter-coupled pair of transistors biased in a nonsaturated region of their operating characteristic and responsive to the quantized output signal for producing an enhanced quantized output signal.

2. A quantizer as claimed in claim 1 wherein the first pair of transistors is of a first conductivity type, and the second pair of transistors is of a second conductivity type.

3. A quantizer as claimed in claim 2 wherein the first pair of transistors is interconnected directly with the second pair of transistors without any level shifting circuitry.

4. A quantizer as claimed in claim 1,2 or 3 wherein the first and second pairs of transistors are bipolar transistors.

5. A quantizer as claimed in any preceding claim wherein the first and second pairs of transistors are fabricated as a monolithic integrated circuit.

6. A quantizer as claimed in any preceding claim wherein the first and second pairs of transistors are arranged for operating at frequencies as high as the microwave frequency range.

7. A quantizer as claimed in any preceding claim wherein the output signal has a very high gain.

8. A data quantizer substantially as herein described with reference to the accompanying drawings.