JPS5921171B2 - How to seal semiconductor devices - Google Patents

How to seal semiconductor devices

Info

Publication number
JPS5921171B2
JPS5921171B2 JP10826575A JP10826575A JPS5921171B2 JP S5921171 B2 JPS5921171 B2 JP S5921171B2 JP 10826575 A JP10826575 A JP 10826575A JP 10826575 A JP10826575 A JP 10826575A JP S5921171 B2 JPS5921171 B2 JP S5921171B2
Authority
JP
Japan
Prior art keywords
hole
semiconductor device
sealing
base
container
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10826575A
Other languages
Japanese (ja)
Other versions
JPS5232269A (en
Inventor
富士夫 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10826575A priority Critical patent/JPS5921171B2/en
Publication of JPS5232269A publication Critical patent/JPS5232269A/en
Publication of JPS5921171B2 publication Critical patent/JPS5921171B2/en
Expired legal-status Critical Current

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  • Casings For Electric Apparatus (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の密封方法、特に表面保護が重要で
ある半導体装置の密封方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for sealing a semiconductor device, and particularly to a method for sealing a semiconductor device in which surface protection is important.

まず、現在行なわれている半導体装置に真空パッケージ
ングを施す方法を第1図を用いて述べる。
First, the currently used method of vacuum packaging a semiconductor device will be described with reference to FIG.

半導体装置1を端子2と排気孔3とを有する基台4の片
面に配設し、基台4の外縁部と凹状の金属性容器5の外
縁部とを熔接により密着接合し、その後排気孔3を通じ
て容器5の内部を真空に引き、しかる後、排気孔3を圧
着等の方法で封じ切る。なお、6は半導体装置1と端子
2を接続する導線である。このような真空封じ方法は金
属容器の真空管の封じ方法と同様であつて、容器のコス
トが大きくなり、また大量生産を行なうのにも不便な方
法であつた。本発明は上述の不都合を排除するために、
半導体装置に貫通孔を設けることにより、量産に向いた
半導体装置密封方法を提供することを目的とする。
The semiconductor device 1 is disposed on one side of a base 4 having terminals 2 and an exhaust hole 3, the outer edge of the base 4 and the outer edge of a concave metal container 5 are tightly joined by welding, and then the exhaust hole is closed. 3, the inside of the container 5 is evacuated, and then the exhaust hole 3 is sealed off by crimping or the like. Note that 6 is a conductive wire that connects the semiconductor device 1 and the terminal 2. Such a vacuum sealing method is similar to the method for sealing vacuum tubes in metal containers, which increases the cost of the container and is also inconvenient for mass production. In order to eliminate the above-mentioned disadvantages, the present invention has the following features:
An object of the present invention is to provide a method for sealing a semiconductor device suitable for mass production by providing a through hole in the semiconductor device.

以下、図面とともに本発明の実施例について説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図および第3図は本発明の一実施例を説明するもの
であつて、11は一部に凹部12を設けた凹状容器とし
てのセラミック等より成る板状の絶縁物基台であり、そ
の表面には導線としての金属層13が印刷等の方法で設
けられている。
FIGS. 2 and 3 illustrate an embodiment of the present invention, in which 11 is a plate-shaped insulating base made of ceramic or the like, which serves as a concave container with a concave portion 12 provided therein; A metal layer 13 as a conductive wire is provided on the surface by a method such as printing.

平板状の半導体装置14は素子等が配設されている保護
すべき面15を基台11の凹部12に対応させて取り付
けられるのであるが、この半導体装置14の特定の個所
には装置の表裏に貫通する貫通孔16が形成されており
、また半導体装置14の保護面15の素子に対する端子
にはハンダバンプ17を設けてある。貫通孔16を半導
体装置14に形成する方法としては、通常のフォトレジ
ストによる表面被覆を半導体装置14の表裏に施し、必
要な貫通孔のパターン形成を行つた後に表裏より同時に
化学エッチングするのが比較的実用的な方法である。さ
て、上記の構造を有する半導体装置14を密封するには
、まず半導体装置14の保護面15を基台11の凹部1
2に対応して設置し、それぞれの外縁部をガラス粉末等
で熱融解等の手段で密封して基台11と半導体装置14
との間の気密性を保つ。
The flat semiconductor device 14 is mounted so that the surface 15 to be protected on which elements and the like are disposed corresponds to the recess 12 of the base 11. A through hole 16 is formed through the semiconductor device 14, and solder bumps 17 are provided at terminals for the elements on the protective surface 15 of the semiconductor device 14. A comparative method for forming the through holes 16 in the semiconductor device 14 is to coat the front and back surfaces of the semiconductor device 14 with ordinary photoresist, form a pattern of the necessary through holes, and then perform chemical etching from the front and back sides at the same time. This is a practical method. Now, in order to seal the semiconductor device 14 having the above structure, first the protective surface 15 of the semiconductor device 14 is placed in the recess 1 of the base 11.
The base 11 and the semiconductor device 14 are installed corresponding to the base 11 and the semiconductor device 14 by sealing their respective outer edges with glass powder or the like by thermal melting or the like.
maintain airtightness between

次に、このような基台11と半導体装置14との合体物
を真空容器内に入れて排気作業に入るのであるが、この
時に多くの合体物を真空容器内に入れておくだけですべ
て同様に排気することができる。基台11の凹部12中
の排気は半導体装置14の貫通孔16を介して行なわれ
る。ここで、貫通孔16の上縁は皿状に面取りし、且つ
その面に金属層を被着し、その皿状の部分にハンダある
いはガラス等より成る封口体18を設置しておくことは
排気および後の密封工程に際して非常に便利なものとな
る。この部分の詳細については後に述べることにする。
次に、先述の合体物を貫通孔16を介して排気するので
あるが、合体物が貫通孔16の上縁に封口体18を有す
るようなものであれば、貫通孔16の上縁と封口体18
とは排気抵抗が小さくなるような形状にしておく必要が
ある。
Next, the combination of the base 11 and the semiconductor device 14 is placed in a vacuum container and the exhaust work begins. can be exhausted. The recess 12 of the base 11 is evacuated through the through hole 16 of the semiconductor device 14 . Here, the upper edge of the through hole 16 is chamfered into a dish shape, a metal layer is applied to that surface, and a sealing body 18 made of solder or glass is installed in the dish-shaped part. This is very convenient for the subsequent sealing process. The details of this part will be described later.
Next, the above-mentioned combined object is evacuated through the through hole 16. If the combined object has a sealing body 18 on the upper edge of the through hole 16, the upper edge of the through hole 16 and the sealing body are removed. body 18
The shape must be such that the exhaust resistance is small.

排気終了後、真空容器内で貫通孔16を加熱熔解して封
口するかもしくは貫通孔16の上縁と封口体18とを加
熱により熔解させて貫通孔16を気密封口する。加熱方
法としては、熱、光の照射あるいはコイルによる誘導加
熱等で行なうことができる。第3図は封口体18により
気密封口された状態を示す。このようにして、基台11
と半導体素子14の機能素子の部分は完全に密封された
ことになる。ところで、基台11の凹部12の体積とし
ては小さなもので十分であり、この様な密封方法は特に
混成集積回路装置の如く大面積の絶縁物基板上に多くの
機能素子や回路網を集積する場合には特に有効ね密封方
法である。更に半導体装置の外面に対しては保護のため
に附加的なパツケージングを施す事は任意である。さて
ここで、先に述べておいた半導体装置14の貫通孔16
と封口体18について詳細に述べる。
After the evacuation is completed, the through hole 16 is sealed by heating and melting in the vacuum container, or the upper edge of the through hole 16 and the sealing body 18 are heated and melted to seal the through hole 16 hermetically. As a heating method, heat, light irradiation, induction heating using a coil, etc. can be used. FIG. 3 shows a state in which the opening is hermetically sealed by the sealing body 18. In this way, the base 11
This means that the functional element portion of the semiconductor element 14 is completely sealed. By the way, a small volume of the recess 12 of the base 11 is sufficient, and this type of sealing method is particularly useful when many functional elements and circuit networks are integrated on a large-area insulating substrate, such as in a hybrid integrated circuit device. This is a particularly effective sealing method in some cases. Furthermore, it is optional to provide additional packaging to the outer surface of the semiconductor device for protection. Now, the through hole 16 of the semiconductor device 14 mentioned earlier
The sealing body 18 will be described in detail.

第4図は半導体装置14の要部断面図を示すものであり
、19は貫通孔16の上縁に形成された皿部である。第
5図、第6図は半導体装置14と封口体18の斜視図で
、皿部19の内面にはニツケル等により金属メツキの施
された被膜が被着されている。排気作業時には封口体1
8と皿部19の間隙より排気が行なわれるので、それぞ
れの形状を排気抵抗が減少するように形成しなければい
けない。封口体18として球状体のものを用いた場合に
は、皿部19は第5図に示すように角錐状のもの、ある
いは第6図に示すように花弁状等に形成すれば排気抵抗
は減少する。また、皿部19として円錐状のものを形成
した場合には、封口体18としては立方体あるいは四面
体等のものを用いるのが望ましい。第7図は本発明の他
の実施例で、圧力センサとしての半導体装置を封口体を
用いて真空封じする方法を示すものである。
FIG. 4 shows a sectional view of a main part of the semiconductor device 14, and 19 is a plate portion formed at the upper edge of the through hole 16. As shown in FIG. 5 and 6 are perspective views of the semiconductor device 14 and the sealing body 18, and the inner surface of the dish portion 19 is coated with a metal-plated film made of nickel or the like. Sealing body 1 during exhaust work
Since exhaust is performed through the gap between the plate 8 and the dish portion 19, the shape of each must be formed so as to reduce the exhaust resistance. When a spherical sealing body 18 is used, the exhaust resistance can be reduced by forming the plate 19 into a pyramid shape as shown in FIG. 5, or a petal shape as shown in FIG. do. Further, when the dish portion 19 is formed into a conical shape, it is desirable to use a cube, a tetrahedron, or the like as the sealing body 18. FIG. 7 shows another embodiment of the present invention, which shows a method for vacuum-sealing a semiconductor device as a pressure sensor using a sealing body.

同図において、21は凹部22を有する凹状の容器とし
てのセラミツク等の絶縁物よりなる基台であつて、貫通
孔23と抵抗層24,25とを備えた半導体装置26の
外縁部が容器21の外縁部とガラス等により接合部27
で密封されている。28は抵抗層24,25を接続する
ための金属層、29は外部導出線である。
In the figure, reference numeral 21 denotes a base made of an insulating material such as ceramic as a concave container having a concave portion 22, and the outer edge of a semiconductor device 26 having a through hole 23 and resistance layers 24 and 25 is connected to the container 21. The joint part 27 is formed by the outer edge of the glass, etc.
is sealed. 28 is a metal layer for connecting the resistance layers 24 and 25, and 29 is an external lead line.

圧力センサは半導体装置26に加えられる応力による歪
量が可能な限り均一であることが強度上、計測上からも
望ましいため、容器21の凹部22の形状も単純な形状
が良く、また貫通孔23も抵抗層24,25から可及的
に離す方が良い。そのため、貫通孔23と凹部22を連
絡する溝30を基板21に形成しておく必要がある。溝
30を設けることにより、凹部22の排気は溝30、貫
通孔23を介して行ない、排気作業後貫通孔23の上縁
の皿部を封口体で熔解して気密封じする。以上のように
して気密封じされた圧力センサは、凹部22が真空であ
るので絶対圧センサとして用いることができ、抵抗層2
4に負圧を加えることにより圧力の測定が行なわれる。
It is desirable for the pressure sensor to have as uniform an amount of strain as possible due to the stress applied to the semiconductor device 26 from the viewpoint of strength and measurement. It is also better to separate them from the resistance layers 24 and 25 as much as possible. Therefore, it is necessary to form a groove 30 in the substrate 21 that connects the through hole 23 and the recess 22. By providing the groove 30, the concave portion 22 is evacuated via the groove 30 and the through hole 23, and after the evacuation operation, the dish portion at the upper edge of the through hole 23 is melted with a sealing material to seal it airtight. The pressure sensor hermetically sealed as described above can be used as an absolute pressure sensor because the recess 22 is in a vacuum, and the resistance layer 2
Pressure measurement is performed by applying negative pressure to 4.

第8図は本発明を圧力センサに用いた更に他の実施例を
示す図で、第7図と同一のものには同一番号を付してあ
る。
FIG. 8 is a diagram showing still another embodiment in which the present invention is applied to a pressure sensor, in which the same parts as in FIG. 7 are given the same numbers.

第8図に示すセラミツク等の絶縁物よりなる基台21に
は2段の凹部が形成されており、下方の凹部22は今ま
で述べてきた真空のためのスペースで、上方の凹部は半
導体装置26を収納する空間となつている。半導体装置
26と基台21とは接合部27で気密封じをしてあり、
前の実施例に比して本実施例の方が封じの作業は容易で
ある。また、基台21が2段構造の凹部を備えているた
め半導体装置26と基台21との合体物の表面はフラツ
トになる利点を有している。本実施例の装置では、貫通
孔23とは独立した貫通孔31を備えており、貫通孔2
3は金属層28を被着することにより抵抗層24と同2
5とを接続することができ、貫通孔31は同様に金属層
28を被着することにより抵抗層25と外部導出線29
とを接続することができる。半導体装置26と基台21
とを接合する時に貫通孔31が封口できるように接合す
れば、溝は貫通孔23の下部と凹部22の間に形成すれ
ば良い。以上のようにして合体物を形成した後、貫通孔
23と溝30とを介して凹部22の内部を排気し、その
後貫通孔23の上縁の皿部を熔解封じする。以上のよう
にして気密封じされた圧力センサも前実施例と同様にし
て抵抗層24に負圧を加えることにより絶対圧センサと
して利用することができる。
A base 21 made of an insulating material such as ceramic as shown in FIG. 8 has two recesses formed therein. The lower recess 22 is a space for the vacuum mentioned above, and the upper recess is a space for semiconductor devices. It is a space to store 26. The semiconductor device 26 and the base 21 are hermetically sealed at a joint 27.
The sealing work in this embodiment is easier than in the previous embodiment. Furthermore, since the base 21 has a two-tiered concave structure, the combined surface of the semiconductor device 26 and the base 21 has the advantage of being flat. The device of this embodiment has a through hole 31 independent of the through hole 23, and the through hole 2
3 is the same as the resistance layer 24 by depositing the metal layer 28.
5 can be connected to the resistance layer 25 and the external lead wire 29 by similarly covering the metal layer 28 to the through hole 31.
and can be connected. Semiconductor device 26 and base 21
The groove may be formed between the lower part of the through hole 23 and the recess 22 if they are joined so that the through hole 31 can be sealed. After forming the combined object as described above, the inside of the recess 22 is evacuated through the through hole 23 and the groove 30, and then the dish portion at the upper edge of the through hole 23 is sealed by melting. The pressure sensor hermetically sealed as described above can also be used as an absolute pressure sensor by applying negative pressure to the resistance layer 24 in the same manner as in the previous embodiment.

これまで述べてきた実施例では凹状容器の内部を真空に
する方法で述べてきたが、本発明は特にこれに限定する
ものではなく、凹状容器内部を希ガス等の他の気体と置
換する場合にも可能な方法である。
In the embodiments described so far, a method has been described in which the inside of the concave container is evacuated, but the present invention is not particularly limited to this. This is also a possible method.

以上説明してきたように、表裏面に貫通孔を有する半導
体素子の外縁部と凹状容器の外縁部とを密着接合した後
、前記凹状容器内を前記貫通孔を介して排気し、しかる
後に前記貫通孔を封口することを特徴とする本発明の半
導体装置の密封方法は、小さな体積の凹部を有する簡単
な凹状容器で半導体装置を保護できるため容器のコスト
が少なくて済み、半導体装置自身に排気通路であり、か
つ容易に封口できる貫通孔が形成されているため大量の
半導体装置を排気できるので量産向きであり、また貫通
孔を表裏間の電気的接続経路として利用できるもので、
混成集積回路の気密封じには特に有効で、非常に工業的
価値の高いものである。
As explained above, after the outer edge of the semiconductor element having through holes on the front and back surfaces and the outer edge of the concave container are closely joined together, the interior of the concave container is evacuated through the through hole, and then the through hole is The method for sealing a semiconductor device of the present invention, which is characterized by sealing a hole, can protect the semiconductor device with a simple concave container having a small-volume concave portion, thereby reducing the cost of the container and providing an exhaust passage in the semiconductor device itself. Moreover, since it has a through hole that can be easily sealed, it is suitable for mass production because it can exhaust a large amount of semiconductor devices, and the through hole can be used as an electrical connection path between the front and back sides.
It is particularly effective for hermetically sealing hybrid integrated circuits, and has extremely high industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置を気密封じする時の構造を示
す断面図、第2図、第3図は本発明の半導体装置の密封
方法の一実施例を示す図、第4図、第5図、第6図は貫
通孔の封口部分を示す図、第7図は本発明の半導体装置
の密封方法の他の実施例を示す図、第8図は本発明の半
導体装置の密封方法の更に他の実施例を示す図である。 11,21・・・・・・基台、12,22・・・・・・
凹部、13,28・・・・・・金属層、14,26・・
・・・・半導体装置、16,23,31・・・・・・貫
通孔、27・・・・・・接合部、29・・・・・・外部
導出線。
FIG. 1 is a cross-sectional view showing a structure when a conventional semiconductor device is hermetically sealed, FIGS. 2 and 3 are views showing an embodiment of the method for sealing a semiconductor device of the present invention, and FIGS. 6 shows a sealing portion of a through hole, FIG. 7 shows another embodiment of the method for sealing a semiconductor device according to the present invention, and FIG. 8 shows a further example of the method for sealing a semiconductor device according to the present invention. It is a figure which shows another Example. 11, 21... Base, 12, 22...
Recessed portion, 13, 28... Metal layer, 14, 26...
... Semiconductor device, 16, 23, 31 ... Through hole, 27 ... Joint part, 29 ... External lead wire.

Claims (1)

【特許請求の範囲】[Claims] 1 表裏間に貫通孔を有する半導体素子の外縁部と凹状
容器の外縁部とを密着接合した後、前記凹状容器内を前
記貫通孔を介して排気し、しかる後に前記貫通孔を封口
することを特徴とする半導体装置の密封方法。
1. After closely joining the outer edge of a semiconductor element having a through hole between the front and back sides and the outer edge of a concave container, the inside of the concave container is evacuated through the through hole, and then the through hole is sealed. Characteristic method for sealing semiconductor devices.
JP10826575A 1975-09-05 1975-09-05 How to seal semiconductor devices Expired JPS5921171B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10826575A JPS5921171B2 (en) 1975-09-05 1975-09-05 How to seal semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10826575A JPS5921171B2 (en) 1975-09-05 1975-09-05 How to seal semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5232269A JPS5232269A (en) 1977-03-11
JPS5921171B2 true JPS5921171B2 (en) 1984-05-18

Family

ID=14480259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10826575A Expired JPS5921171B2 (en) 1975-09-05 1975-09-05 How to seal semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5921171B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153976A (en) * 2008-12-24 2010-07-08 Epson Toyocom Corp Piezoelectric device and method of manufacturing the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2710986B2 (en) * 1989-05-23 1998-02-10 新光電気工業株式会社 Electronic equipment
US6036872A (en) * 1998-03-31 2000-03-14 Honeywell Inc. Method for making a wafer-pair having sealed chambers
AU2003228973A1 (en) * 2002-05-07 2003-11-11 Memgen Corporation Electrochemically fabricated hermetically sealed microstructures
JP4665959B2 (en) 2007-11-30 2011-04-06 日本電気株式会社 Vacuum package
JP2014036081A (en) * 2012-08-08 2014-02-24 Seiko Epson Corp Method for manufacturing electronic device, electronic device, electronic equipment, and movable body
JP6439272B2 (en) * 2014-04-23 2018-12-19 セイコーエプソン株式会社 Package, electronic device, method for manufacturing electronic device, electronic apparatus, and moving body

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153976A (en) * 2008-12-24 2010-07-08 Epson Toyocom Corp Piezoelectric device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS5232269A (en) 1977-03-11

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