JPS59211137A - Comparison system - Google Patents

Abstract

PURPOSE:To realize an operation to supply two operands as they are in a logic comparison processing mode and another operation to supply the two operands after inverting only the code bits of these operands in an arithmetic comparison processing mode, by constituting a comparator only of a logic comparison function. CONSTITUTION:A logic comparator 4 has only output functions for coincidence (=), larger (>) and smaller (<) states, respectively. Both the 1st and 2nd operand data 1 and 2 are supplied to the comparator 4 via exclusive OR circuit 3 and 3, respectively. An arithmetic comparison signal C is used as an input of the other side of the circuit 3. The data 1 and 2 are supplied to the comparator 4 as they are if they are logic data. While the signal C is applied to the comparator 4 in the form of a signal obtained by inverting only the code bit in the case of the arithmetic data. Thus it is possible to perform a comparison operation between the arithmetic data and the logic data through a single comparator.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a comparison circuit for a data processing device, and particularly to a system for realizing logical comparison and arithmetic comparison processing with a small number of circuits.

Technical Background One of the functions operated by a data processing device is a comparison calculation function. A method is to prepare a dedicated circuit (sometimes one is a dedicated circuit and the other is shared), and the circuit is switched by a control signal to distinguish between arithmetic comparison processing and logical comparison processing, a comparison function and a bit inspection function, etc. By setting up a circuit that mixes
The most common method is to use a control signal that is suitable for the circuit, and in either case it depends on the amount of hardware.

As the number of logic stages increases or the control method becomes complicated,
A systematic improvement was desired.

IcI Prior Art and Problems An example of the prior art is shown in FIG. As is clear from this figure, two operands are input to the comparator, and two control signals for logical comparison and arithmetic comparison are input from the outside. Therefore, the comparison circuit is also realized with a configuration that includes two types of comparison circuits that can perform each type of comparison, for example, logical comparison and arithmetic comparison, and the number of circuits increases.
The number of logic stages from inputting operand data to obtaining a comparison result also increases, resulting in an increase in the amount of hardware and calculation time.

+dl OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide an operand data comparison method that can reduce the amount of hardware and the number of logic stages.

tel Structure of the invention And this purpose, according to the invention, is a logical comparison.

In a data processing device that performs arithmetic comparison processing, when performing logical comparison processing, two operands are input to the side comparison circuit, and when performing arithmetic comparison processing, only the sign bits of the two operands are inverted and input, and the above comparison circuit is inputted. This is achieved by providing a method consisting of a comparison circuit that is realized only with a logical comparison function, which makes it possible to simplify the comparison circuit and shorten the calculation time.

(f) Examples of the Invention The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a diagram for explaining the present invention in detail with respect to arithmetic data, that is, signed data and logical data, and FIG. 3 is a diagram for explaining one embodiment of the present invention.

(A) in FIG. 2 shows signed data, and the data string on the left is a data string when the present invention is not implemented.

In the case of signed data, the most significant bit is the sign bit, which indicates the maximum negative value of the binary number (=2 to the 31st power). Therefore, if the top focus is "0", the maximum negative value will be multiplied by 0, resulting in positive data, the maximum value will be 011-1, and the values will become smaller sequentially. 000-1. And it becomes ooo-o which is zero.

The next data is 11-
1 (2 to the 31st power - 1), the result is -1, which gradually decreases to the maximum negative value of 100 -
It has been shown that the value is 0. If only the sign bit of this signed data is inverted, the data string shown on the right side is obtained, and it can be understood that it is a data string from the maximum value to the minimum value of the logical data.

(b) in FIG. 2 is logical data, and since all of the data from the least significant bit to the most significant bit is binary data, its maximum value is 111-1.

The minimum value is ooo-o, and it is sufficient to compare the sizes of the data strings on that side.

The present invention was made by paying attention to the above-mentioned characteristics of signed data and logical data, and FIG. 3 shows one embodiment thereof.

In the drawing, 1 is the first operand data, 2 is the second operand data, 3 is the exclusive OR circuit, and 4 is the comparator, which indicates a match output (-), a larger output (>), and a smaller output (<).
Output.

In this figure, first operand data 1. The second operand data 2 is input as arithmetic data, and the control unit (
When an arithmetic comparison signal C is inputted from (not shown), the exclusive OR circuit 3 performs an exclusive OR of the sign bit (most significant bit) of the operand data and the control signal C.
Only the sign bits of the first and second operand data are inverted, the other bits are input to the comparator 4, and the two arithmetic data are treated as logical data and compared.

When the 1.2nd operand data is logical data, the control signal C sent from the control section is not an arithmetic comparison signal, so the most significant bit of the logical data at this time is not inverted and compared. The two logical data are input to the device 4, and the two logical data are compared.

The comparator referred to here may be realized by an arithmetic circuit mainly consisting of an adder, or it may be realized by a dedicated circuit that sequentially scans bits from the uppermost bit and compares the magnitude. No matter the means used, there will be no impediment to the implementation of the present invention.

(a) Effects of the Invention As explained in detail above, according to the present invention, a control signal is sent to a single comparator for comparing logical data and comparing arithmetic data to distinguish whether it is an arithmetic comparison or a logical comparison. When performing an arithmetic comparison, the most significant bit (sign bit) of the two operand data is inverted and the arithmetic data is treated the same as logical data, making it easy to perform arithmetic and logical comparisons. This has the effect of reducing the amount of hardware and the number of logical stages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the prior art, FIG. 2 is a diagram illustrating the present invention in detail regarding arithmetic data and logical data, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. In the drawing, 1 is first operand data, 2 is second operand data, and 3 is an exclusive OR circuit. 4 indicates a comparator, and C indicates a control signal indicating an arithmetic operation. - (1 θ 1 Q θ 1 type. - Width 205 - To - \ -1 Momo 1

Claims (1)

[Claims] In a data processing device that performs logical comparison and arithmetic comparison processing, when performing logical comparison processing, two operands are input to the side comparison circuit, and when performing arithmetic comparison processing, only the sign focus of the two operands is inverted and input; A comparison method characterized in that the comparison circuit is constituted by a comparison circuit realized only with a logical comparison function.