JPS59208945A - Prescaler circuit - Google Patents

Prescaler circuit

Info

Publication number
JPS59208945A
JPS59208945A JP58083534A JP8353483A JPS59208945A JP S59208945 A JPS59208945 A JP S59208945A JP 58083534 A JP58083534 A JP 58083534A JP 8353483 A JP8353483 A JP 8353483A JP S59208945 A JPS59208945 A JP S59208945A
Authority
JP
Japan
Prior art keywords
circuit
frequency
signal
selection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58083534A
Other languages
Japanese (ja)
Inventor
Yoshitaka Kitada
北田 義孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58083534A priority Critical patent/JPS59208945A/en
Publication of JPS59208945A publication Critical patent/JPS59208945A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/38Starting, stopping or resetting the counter

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce the useless working current of a prescaler circuit by stopping the action of a dividing circuit in case a count signal other than a dividing signal is selected by a selecting circuit. CONSTITUTION:An AND gate 3 is connected to the input of a dividing circuit 1, and the output of an AND circuit 3 is always set at logic ''0'' when the logic value of the 2nd selection signal SEL2 is set at ''0''. Thus it is possible to stop the action of the circuit 1 by a means which stops the clock input to the circuit 1. The working current of the AND gate of the means which stops the action of the circuit 1 is very small. Therefore the working current obtained when a dividing signal DIV1 is selected by a selecting circuit 1 is equal to that of a conventional prescaler circuit, i.e., 200muA. However the action of the circuit 1 is stopped when both 1st and 2nd clock inputs CI1 and CIN2 are selected. Thus the power consumption of the dividing circuit 1 is reduced almost down to ''0''. As a result, the working current is reduced down to about 1/10, i.e., 20muA.

Description

【発明の詳細な説明】 本発明は、集積回路特に0M08回路で構成される集積
回路に内蔵するタイマ回路のプリスケーラに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a prescaler for a timer circuit built into an integrated circuit, particularly an integrated circuit composed of 0M08 circuits.

近年、水晶発振器の発振出力や商用周波数を直接又は分
周してカウントし、所定の時間ごとに所定のタイマ動作
を行うタイマ回路を内蔵した時計用集積回路やマイクロ
コンピュータが急速に普及している。これらのタイマ回
路は、通常グリスケーラ回路とカウント回路とにて構成
されておシ、ブリスケ−2回路唸周波数の異る複数のク
ロック信号や水晶発振器の発振出力や、前記発振出力の
分局を行い、周波数を低下させたクロック信号の中から
1つを選択し、カウント回路の基準クロック信号を出力
する回路であシ、カウント回路は前記基準クロック信号
に同期してカウント動作を行うカウンターで、カウント
値が所定の設定値に達した時、所定のタイマ動作を行う
In recent years, clock integrated circuits and microcomputers that have a built-in timer circuit that counts the oscillation output of a crystal oscillator or a commercial frequency directly or by dividing it, and performs a predetermined timer operation at predetermined intervals have rapidly become popular. . These timer circuits are usually composed of a grease scaler circuit and a count circuit, and output a plurality of clock signals with different beat frequencies or the oscillation output of a crystal oscillator, and branch out the oscillation output. This is a circuit that selects one of the clock signals whose frequency has been lowered and outputs a reference clock signal for the count circuit.The count circuit is a counter that performs a counting operation in synchronization with the reference clock signal, and the count value is When reaches a predetermined set value, a predetermined timer operation is performed.

一般にタイマ回路を内蔵した集積回路はタイマによって
設定された所定時間ごとの間はり動作を行っているため
に動作電流は比較的少く、電池による動作が可能である
。そこで、タイマ回路を内蔵した集積回路を電池によっ
て少しでも長い時間動作させるために動作電流の少いタ
イマ回路が必要とされている。
Generally, an integrated circuit with a built-in timer circuit performs a periodic operation at predetermined time intervals set by the timer, so the operating current is relatively small, and the integrated circuit can be operated using a battery. Therefore, in order to operate an integrated circuit containing a timer circuit using a battery for as long as possible, a timer circuit with a small operating current is required.

従来のグリスケ−2回路を第1図に示す。A conventional Gliske-2 circuit is shown in FIG.

CINIは第1のクロック入力、ClN2は第2のクロ
ック入力、1は分周回路、2は選択回路、DIvlは分
周信号、5EL1.5EL21dそtLぞれ第1、第2
の選択信号、POUTはグリスケーラ出力を示す。分周
回路1は第1のクロック人力CINIを入力として、分
周動作をし分周信号DIVIを出力する。選択回路2は
第1のクロック人力CINI及び第2のクロック人力C
lN2及び分周信号DIVIを入力とし、第1及び第2
の選択信号5ELI及び5EL2によって前記3人力の
うちのいずれかを選択し、グリスケーラ出力POUTを
出力する。
CINI is the first clock input, ClN2 is the second clock input, 1 is the frequency divider circuit, 2 is the selection circuit, DIvl is the frequency division signal, 5EL1.5EL21dSotL are the first and second clock inputs, respectively.
The selection signal POUT indicates the grease scaler output. The frequency dividing circuit 1 receives the first clock manually input CINI, performs a frequency dividing operation, and outputs a frequency divided signal DIVI. The selection circuit 2 has a first clock input CINI and a second clock input C.
lN2 and the frequency divided signal DIVI as input, and the first and second
One of the three manual inputs is selected by the selection signals 5ELI and 5EL2, and the grease scaler output POUT is output.

従来のグリスケーラ回路は、選択回路2によって第1の
クロック人力CINI又は第2のクロック人力ClN2
が選択された場合、すなわち分局信号DIVIが選択さ
れなかった場合、においても分周回路1には第1のクロ
ック人力CINIが入力されておシ、分周回路1は分周
動作をしていたため、分周回路1で不必要な電流を必要
としていた。
The conventional grease scaler circuit selects either the first clock input CINI or the second clock input ClN2 by the selection circuit 2.
is selected, that is, when the division signal DIVI is not selected, the first clock manually input CINI is input to the frequency divider circuit 1, and the frequency divider circuit 1 is performing frequency dividing operation. , the frequency divider circuit 1 required unnecessary current.

本発明の目的は無駄な電流を必要としないグリスケーラ
回路を提供することにある。
An object of the present invention is to provide a grease scaler circuit that does not require unnecessary current.

本発明は、CMO8回路の動作電流は、その回路の動作
周波数に比例して増加するので、動作周波数を0にして
動作を停止すれば、動作電流はリーク電流程度に少くな
る原理に基き、分周回路の分局信号以外の信号が選択回
路で選択された場合は分周回路の動作を停止せしめる。
The present invention is based on the principle that the operating current of a CMO8 circuit increases in proportion to the operating frequency of the circuit, so if the operating frequency is set to 0 and the operation is stopped, the operating current decreases to the level of leakage current. When a signal other than the division signal of the frequency circuit is selected by the selection circuit, the operation of the frequency division circuit is stopped.

本発明のプリスケーラ回路は、少くともカウント信号を
入力とし、その周波数を分周して分周信号を出力する分
周回路と、前記分周信号と1つ以上の任意のカウント信
号とのいずれかを選択して出力する選択回路とを具備し
、前記選択回路によって前記分周信号以外のカウント信
号が選択された場合に前記分周回路の動作を停止する手
段を有することを特徴としている。
The prescaler circuit of the present invention includes a frequency dividing circuit that receives at least a count signal, divides its frequency and outputs a frequency-divided signal, and a frequency divider circuit that receives at least a count signal and outputs a frequency-divided signal; and a selection circuit that selects and outputs the frequency division signal, and includes means for stopping the operation of the frequency division circuit when a count signal other than the frequency division signal is selected by the selection circuit.

以下図面を参照して本発明の実施例について説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図は第1の実施例のグリスグー2回路のブロック図
で、3はアンドゲートを示し、従来のグリスケーラ回路
を示した第1図と同一の図番を付したものは、従来の回
路と動作が同一のため説明は省略する。アンドゲート3
は、第2の選択信号5EL2と第1のクロック人力CI
NIとを入力とし、入力の論理積をとり、分周回路1に
出力する。分周回路1は、アンドゲート3の出力を分周
し、分周信号り工V1を出力する。
FIG. 2 is a block diagram of the grease goo 2 circuit of the first embodiment, where 3 indicates an AND gate, and the same numbers as in FIG. 1, which shows the conventional grease scaler circuit, are the same as the conventional circuit. Since the operations are the same, the explanation will be omitted. and gate 3
is the second selection signal 5EL2 and the first clock input CI
NI is taken as an input, the logical product of the inputs is taken, and the result is output to the frequency dividing circuit 1. The frequency dividing circuit 1 divides the frequency of the output of the AND gate 3 and outputs a frequency divided signal V1.

選択回路2は、第1のクロック人力CINI及び第2の
クロック人力ClN2及び分周信号DIVIを入力とし
、第1及び第2の選択信号5ELI及び8EL2に従っ
て、前記3人力のうち1つを選択してグリスケーラ出力
POUTに出力する。
The selection circuit 2 inputs the first clock input CINI, the second clock input ClN2, and the divided signal DIVI, and selects one of the three inputs according to the first and second selection signals 5ELI and 8EL2. and output to the grease scaler output POUT.

第1表は、選択回路2の動作を示す真理値表で、選択回
路2は第1の選択信号5ELLが論理値0で第2の選択
信号5EL2が論理値Oの時は第1のクロック人力CI
NIを選択し、第1の選択信号5ELIが論理値1で、
第2の選択信号SEI、2が論理値0の時は、第2のク
ロック入力ClN2を選択し、第2の選択信号8EL2
の論理値が1の時は、第1の選択信号5ELIの論理値
にかかわらず分周信号DIVIを選択し出力する。
Table 1 is a truth table showing the operation of the selection circuit 2. When the first selection signal 5ELL has a logic value of 0 and the second selection signal 5EL2 has a logic value of 0, the selection circuit 2 uses the first clock manually. C.I.
NI is selected, the first selection signal 5ELI has a logic value of 1,
When the second selection signal SEI,2 has a logic value of 0, it selects the second clock input ClN2, and the second selection signal 8EL2
When the logical value of is 1, the divided signal DIVI is selected and output regardless of the logical value of the first selection signal 5ELI.

第2の選択信号8EL2が論理値0の時は、分周回路1
の分周出力DIVIは選択されない。
When the second selection signal 8EL2 has a logic value of 0, the frequency dividing circuit 1
The divided output DIVI of is not selected.

従って、分周回路の動作を停止したとしてもプリスケー
ラの動作には何の支障もないことは明白である。
Therefore, it is clear that even if the operation of the frequency divider circuit is stopped, there is no problem in the operation of the prescaler.

第1の実施例のプリスケーラ回路においては、分周回路
1の入力にアンドゲート3を接続しておシ、第2の選択
信号5EL2の論理値が0の時はアンドゲート3の出力
は常に論理値0となるため、分周回路1へのクロック入
力を停止する手段によって分周回路1の動作を停止させ
ることができる。
In the prescaler circuit of the first embodiment, an AND gate 3 is connected to the input of the frequency dividing circuit 1, and when the logic value of the second selection signal 5EL2 is 0, the output of the AND gate 3 is always logic. Since the value becomes 0, the operation of the frequency dividing circuit 1 can be stopped by means of stopping the clock input to the frequency dividing circuit 1.

また、分周回路1の動作を停止させる手段は上記の手段
に限定されず、分周回路1の初期化を行うリセット信号
をオリ用して、分周回路1の動作を停止することも可能
である。
Further, the means for stopping the operation of the frequency dividing circuit 1 is not limited to the above-mentioned means, and it is also possible to stop the operation of the frequency dividing circuit 1 by using a reset signal that initializes the frequency dividing circuit 1. It is.

ここで、実際に本発明を応用した結果を述べると本発明
の第1の実施例のグリスケーラ回路において、第1のク
ロック人力CINIの周波数ij:400kl(zであ
シ第2のクロック入力ClN2の周波数は50H2であ
ジ、分周回路1は8段のバイナリ(2進)カウンタで構
成されている。
Here, to describe the result of actually applying the present invention, in the grease scaler circuit of the first embodiment of the present invention, the frequency ij of the first clock input CINI: 400kl (z) and the frequency of the second clock input ClN2. The frequency is 50H2, and the frequency divider circuit 1 is composed of an 8-stage binary counter.

従来のグリスケーラ回路では、プリスケーラ出力POU
Tにどのイ1′号を選択して出力した場合てらっても、
常に分周回路が動作する構成であったため、グリスケー
ラ回路全体の動作電流を測定した結果は200μAで、
グリスケーラ出力POU’L’に出力される信号に依存
しなかった。
In the conventional grease scaler circuit, the prescaler output POU
Even if you select which A1' and output it to T,
Since the frequency divider circuit was always in operation, the operating current of the entire grease scaler circuit was measured to be 200 μA.
It did not depend on the signal output to the grease scaler output POU'L'.

しかし本発明の第1の実施例においては、分周回路の動
作を停止する手段のアンドゲートの動作電流はごく小さ
いので、選択回路1で分周信号DIVIを選択した場合
の動作電流は従来のグリスケーラ回路と同一で200μ
人であったが、第1及び第2のクロック入力ClN2を
選択した場合は、分周回路1の動作は停止し分周回路1
による消費電流はほとんど0にまで減少するため、動作
電流は約10分の1の20μAにまで減少することが確
認された。すなわち、200μ人と20μAの差の18
0μ人は、分周回路が動作することによる動作電流であ
ることが判明し、本発明によれば無駄な電流を大幅に削
減できる。
However, in the first embodiment of the present invention, the operating current of the AND gate, which is the means for stopping the operation of the frequency dividing circuit, is very small, so when the selection circuit 1 selects the frequency dividing signal DIVI, the operating current is as low as the conventional one. Same as the grease scaler circuit, 200μ
However, if the first and second clock inputs ClN2 are selected, the operation of the frequency divider circuit 1 is stopped and the frequency divider circuit 1
It was confirmed that the operating current was reduced to 20 μA, which is approximately one-tenth, because the current consumption due to the current consumption was reduced to almost 0. In other words, the difference between 200 μA and 20 μA is 18
It has been found that 0μ is an operating current caused by the operation of the frequency dividing circuit, and according to the present invention, unnecessary current can be significantly reduced.

第3図は本発明の第2の実施例のグリスケーラ回路のブ
ロック図で、4はアンドゲート、5は分周回路、6は選
択回路、DIV2は分周信号を示し、第1図及び第2図
と同一の動作をするものについては説明を省略する。
FIG. 3 is a block diagram of a grease scaler circuit according to a second embodiment of the present invention, in which 4 is an AND gate, 5 is a frequency divider circuit, 6 is a selection circuit, and DIV2 is a frequency division signal. Descriptions of components that operate in the same manner as those shown in the figures will be omitted.

第3図は、複数の分周回路が直列に接続されている場合
の実施例である。アンドゲート3は第2の選択信号5E
L2と第1のクロック人力CINIとを入力とし、入力
の論理積をとシ分周回路1に出力する。分周回路1はア
ンドゲート3の出力を分周し分周信号DIVIを出力す
る。アンドゲート4は第1の選択信号5ELIと分周信
号DIVIとの論理積をとり分周回路5に出力する。分
周回路5はアンドゲート4の出力を分周し、分周信号D
IV2を出力する。選択回路6は、第1のクロック人力
CINI及び第2のクロック人力ClN2及び分周信号
DIVI及び分周信号DIV2を入力とし、第1及び第
2の選択信号5BLI及び5EL2に従って前記4人力
のうちの1つを選択してグリスケ−2出力POUTに出
力する。
FIG. 3 shows an embodiment in which a plurality of frequency dividing circuits are connected in series. AND gate 3 is the second selection signal 5E
L2 and the first clock input CINI are input, and the AND of the inputs is output to the frequency dividing circuit 1. The frequency dividing circuit 1 divides the frequency of the output of the AND gate 3 and outputs a frequency divided signal DIVI. The AND gate 4 ANDs the first selection signal 5ELI and the frequency division signal DIVI and outputs it to the frequency division circuit 5. The frequency dividing circuit 5 divides the output of the AND gate 4, and divides the frequency of the divided signal D.
Output IV2. The selection circuit 6 inputs the first clock input CINI, the second clock input ClN2, the frequency division signal DIVI, and the frequency division signal DIV2, and selects one of the four inputs according to the first and second selection signals 5BLI and 5EL2. Select one and output it to GRISK-2 output POUT.

第2表は選択回路6の選択動作を示す真理値表で、第2
の選択信号の論理値が1で、かつ第1の選択信号の論理
値が1の時は、分周信号DIV2を選択する点をのぞい
て、選択回路6は第1の実施例の選択回路2と同一の動
作をする。従って選択回路6は選択回路2と同様に通常
の論理回路で容易に実現できるととは言うまでもない。
Table 2 is a truth table showing the selection operation of the selection circuit 6.
The selection circuit 6 is the same as the selection circuit 2 of the first embodiment, except that when the logical value of the selection signal is 1 and the logical value of the first selection signal is 1, the frequency division signal DIV2 is selected. It works the same as . Therefore, it goes without saying that the selection circuit 6, like the selection circuit 2, can be easily realized using a normal logic circuit.

第3図に示す第2の実施例において第1の選択信号5E
LIの論理値が0で第2の選択信号5EL2の論理値が
0の場合は、第1の実施例と同様にアンドゲート3によ
って分周回路1の動作が停止し、アンドゲート4によっ
て分周回路2の動作が停止するので無駄な動作電流は無
くなる。選択回路6はり四ツク入力1を選択しグリスケ
ーラ出力POUTに出力する。第1の選択信号5ELL
の論理値が1で第2の選択信号5EL2の論理値が0の
場合は、アンドゲート3によって分周回路1の動作が停
止し、分周信号DIVIは出力されなくなる。
In the second embodiment shown in FIG.
When the logical value of LI is 0 and the logical value of the second selection signal 5EL2 is 0, the AND gate 3 stops the operation of the frequency dividing circuit 1, and the AND gate 4 stops the frequency dividing circuit 1, as in the first embodiment. Since the operation of the circuit 2 is stopped, unnecessary operating current is eliminated. The selection circuit 6 selects the four inputs 1 and outputs it to the grease scaler output POUT. First selection signal 5ELL
When the logical value of is 1 and the logical value of the second selection signal 5EL2 is 0, the operation of the frequency dividing circuit 1 is stopped by the AND gate 3, and the frequency dividing signal DIVI is no longer output.

このため、分周回路5も動作が停止するので無駄な動作
電流は無くなる。
Therefore, since the frequency dividing circuit 5 also stops operating, there is no wasted operating current.

選択回路6は第2のクロック人力ClN2を選択してグ
リスケーラ出力POUTに出力する。
The selection circuit 6 selects the second clock input ClN2 and outputs it to the grease scaler output POUT.

第1の選択信号S’ELIの論理値が0で第2の選択信
号8EL2の論理値が1の場合は、分周回路1は動作し
、分周信号DIVIを出力するが、分周回路5はアンド
ゲート4によって動作が停止するので無駄力動作電流は
無く々る。
When the logic value of the first selection signal S'ELI is 0 and the logic value of the second selection signal 8EL2 is 1, the frequency division circuit 1 operates and outputs the frequency division signal DIVI, but the frequency division circuit 5 Since the operation is stopped by the AND gate 4, the wasted operation current is eliminated.

選択回路6は分周信号DIVIを選択し、グリスケーラ
出力POUTに出力する。
The selection circuit 6 selects the frequency-divided signal DIVI and outputs it to the grease scaler output POUT.

第1の選択信号5ELLの論理値が1で、第2の選択信
号8EL2の論理値が1の場合は、分周回路1及び分周
回路5は動作し、それぞれ分周信号DIVI及びDIV
2を出力する。
When the logic value of the first selection signal 5ELL is 1 and the logic value of the second selection signal 8EL2 is 1, the frequency division circuit 1 and the frequency division circuit 5 operate, and the frequency division signals DIVI and DIV
Outputs 2.

選択回路6は分周信号DIV2を選択し、プリスケーラ
出力POUTに出力する。
The selection circuit 6 selects the frequency-divided signal DIV2 and outputs it to the prescaler output POUT.

以上説明した様に、複数の分周回路を直列に接続した構
成を持つグリスケーラ回路においても本発明によれば無
駄な動作電力を削減できる。
As described above, according to the present invention, wasteful operating power can be reduced even in a grease scaler circuit having a configuration in which a plurality of frequency dividing circuits are connected in series.

さらに、複数の分周回路を並列に接続した構成を持つプ
リスケーラ回路においても、選択回路の動作に対応して
、適当力分周回路の動作を停止させる手段を備えれば同
様の効果を持つことは明らかである。
Furthermore, even in a prescaler circuit having a configuration in which a plurality of frequency dividing circuits are connected in parallel, the same effect can be obtained if a means is provided to stop the operation of the force frequency dividing circuit appropriately in response to the operation of the selection circuit. is clear.

本発明は以上説明したように、選択回路で選択される信
号に対応してグリスケーラ回路の動作に支障の無い分周
回路の動作を停止させる手段を有することによってグリ
スケ−2回路の無駄な動作電流を削減する効果がある。
As explained above, the present invention has a means for stopping the operation of the frequency divider circuit that does not affect the operation of the grease scaler circuit in response to the signal selected by the selection circuit, thereby reducing the unnecessary operating current of the grease scaler circuit. It has the effect of reducing

.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のグリスケーラ回路のブロック図、第2図
は本発明第1の実施例のグリスケージ回路のブロック図
、第3図は本発明第2の実施例のプリスケーラ回路のブ
ロック図である。 1.5・・・・・・分周回路、2,6・・・・・・選択
回路、3 、4−−−−1.アンドゲート、CINI、
ClN2・・・・・・クロック入力、DIVE、DIV
2・・・・・・分周信号、8EL1,8EL2・・・・
・・選択信号、POU’l’・・・・・・プリスケーラ
出力。 第 1 図
FIG. 1 is a block diagram of a conventional grease scaler circuit, FIG. 2 is a block diagram of a grease cage circuit according to a first embodiment of the present invention, and FIG. 3 is a block diagram of a prescaler circuit according to a second embodiment of the present invention. . 1.5... Frequency divider circuit, 2, 6... Selection circuit, 3, 4---1. ANDGATE, CINI,
ClN2...Clock input, DIVE, DIV
2... Frequency division signal, 8EL1, 8EL2...
...Selection signal, POU'l'...Prescaler output. Figure 1

Claims (1)

【特許請求の範囲】[Claims] カウント信号分周して分局信号を出力する分周回路と、
前記分周信号と1つ以上の任意のカウント信号とのいず
れかを選択して出力する選択回路とを具備し、前記選択
回路によって前記分周信号以外のカウント信号が選択さ
れた場合に、前記分周回路の動作を停止する手段を有す
ることを特徴とするブリスケ−2回路。
a frequency dividing circuit that divides the frequency of the count signal and outputs a division signal;
a selection circuit that selects and outputs either the frequency division signal and one or more arbitrary count signals, and when a count signal other than the frequency division signal is selected by the selection circuit, the A Briske-2 circuit characterized by having means for stopping the operation of a frequency dividing circuit.
JP58083534A 1983-05-13 1983-05-13 Prescaler circuit Pending JPS59208945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58083534A JPS59208945A (en) 1983-05-13 1983-05-13 Prescaler circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58083534A JPS59208945A (en) 1983-05-13 1983-05-13 Prescaler circuit

Publications (1)

Publication Number Publication Date
JPS59208945A true JPS59208945A (en) 1984-11-27

Family

ID=13805160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58083534A Pending JPS59208945A (en) 1983-05-13 1983-05-13 Prescaler circuit

Country Status (1)

Country Link
JP (1) JPS59208945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001084710A1 (en) * 2000-05-01 2001-11-08 Koninklijke Philips Electronics N.V. Power adaptive frequency divider

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001084710A1 (en) * 2000-05-01 2001-11-08 Koninklijke Philips Electronics N.V. Power adaptive frequency divider
JP2003533084A (en) * 2000-05-01 2003-11-05 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Power adaptive frequency divider

Similar Documents

Publication Publication Date Title
US5025387A (en) Power saving arrangement for a clocked digital circuit
JP2577134B2 (en) Programmable high-speed divider
US4325031A (en) Divider with dual modulus prescaler for phase locked loop frequency synthesizer
US5398007A (en) Low-power baud rate generator including two oscillators
US6009139A (en) Asynchronously programmable frequency divider circuit with a symmetrical output
US4694475A (en) Frequency divider circuit
JPS59208945A (en) Prescaler circuit
US4331926A (en) Programmable frequency divider
US4785468A (en) Intermittent receiver
US4975651A (en) Digital phase locked loop circuit
JPH0439691B2 (en)
US4176517A (en) Integrated circuit for timepiece
US7171577B2 (en) Methods and apparatus for a system clock divider
JPS6356565B2 (en)
US4072904A (en) Presettable rate multiplier
JPH035948Y2 (en)
US4247932A (en) Electronic timepiece
US4468133A (en) Electronic timepiece
JPS5611440A (en) Exposure time control circuit
JPH0682310B2 (en) Operation frequency switching control circuit for arithmetic unit
JPS58207783A (en) Dial pulse generating circuit
JP2961219B2 (en) Semiconductor integrated circuit
JPH0222716A (en) Clock control circuit
JPS645400Y2 (en)
JPH0290337A (en) Monitor timer circuit