JPS59208861A - Sealing structure of integrated circuit - Google Patents
Sealing structure of integrated circuitInfo
- Publication number
- JPS59208861A JPS59208861A JP8375583A JP8375583A JPS59208861A JP S59208861 A JPS59208861 A JP S59208861A JP 8375583 A JP8375583 A JP 8375583A JP 8375583 A JP8375583 A JP 8375583A JP S59208861 A JPS59208861 A JP S59208861A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- sealing frame
- adhesives
- circuit substrate
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
Description
【発明の詳細な説明】 を樹脂封止する実装構造に関するものである。[Detailed description of the invention] This relates to a mounting structure for resin-sealing.
従来の封止枠を使用する封止は、熱硬化型の接着剤を使
用して、封止枠を回路基板上に接着し封止樹脂を封止枠
内に流入させ加熱硬化させるものと、高精度で、封止樹
脂と親和カのない樹脂（例えばシリコーン樹脂）で封止
枠を回路基板に仮固定し、封止樹脂を流入し加熱硬化さ
せる封止構造とが採用されていた。前者は封止樹脂の枠
外流出防止の点では本発明と同等であるが、封止枠な回
路基板に接着するだめの仮接着として例えば１００℃、
３０分の硬化時間が必要でル）リ、更に封止樹脂の硬化
時間として例えば１００°Ｃ、・１時間程が必要である
。このように仮接着にも長時間な心安とすることは同一
装置で枠接着と封止（ν）脂流入を連続的に処理１〜る
のは、装置が極端（（長くなりバッチ処理を１１なわさ
るを得す、装置が抜髄となり結果的にコストアノプの要
因となっていた。Conventional sealing using a sealing frame involves bonding the sealing frame onto the circuit board using a thermosetting adhesive, causing the sealing resin to flow into the sealing frame and curing it by heating. A sealing structure has been adopted in which the sealing frame is temporarily fixed to the circuit board with high precision and a resin that has no affinity with the sealing resin (for example, silicone resin), and the sealing resin is poured in and cured by heating. The former is equivalent to the present invention in terms of preventing the sealing resin from flowing out of the frame, but it is used for temporary bonding at 100°C, for example, to the circuit board that is the sealing frame.
A curing time of 30 minutes is required, and the curing time of the sealing resin is, for example, about 1 hour at 100°C. In this way, it is extremely necessary to continuously process the frame adhesion and sealing (ν) fat inflow in the same equipment for a long time even for temporary adhesion. As a result, the equipment became the main issue and became the cause of Kosutanopu.
一方後者は、同一装置で連続処理可能だが仮固定用樹脂
が高粘度のため、封止枠と回路基板の密閉性が悪く且つ
固定力が弱いため、樹脂流出を完全に防止する事は不可
能で、側止後人間が検査し修正せざるを得なかった。又
封止枠と回路基板は仮固定のままであり、回路基板に反
りの力が加わると封止枠と回路基板が剥離し、信頼性を
損う欠点を有していた。On the other hand, the latter can be processed continuously using the same equipment, but due to the high viscosity of the temporary fixing resin, the sealing between the sealing frame and the circuit board is poor, and the fixing force is weak, so it is impossible to completely prevent the resin from flowing out. So, after the side was stopped, a human had to inspect and correct it. In addition, the sealing frame and the circuit board remain temporarily fixed, and when a warping force is applied to the circuit board, the sealing frame and the circuit board peel off, resulting in a drawback that reliability is impaired.
本発明は上記従来法の欠点を除去し、封止樹脂が封止枠
外の回路基板」二に流出する事を防止し、しかも接着剤
の硬化時間を短く′１−ることによって封止の自動化・
無人化を実現し、低コストのＩＣ制止を行なう事を目的
としたものである。The present invention eliminates the drawbacks of the conventional method described above, prevents the sealing resin from leaking onto the circuit board outside the sealing frame, and automates the sealing by shortening the curing time of the adhesive.・
The purpose is to realize unmanned operation and perform low-cost IC control.
本発明の実施例を図で説明する。Embodiments of the present invention will be explained with figures.
第１図は、本発明の第１実施例を示す断面図、第２図は
封止樹脂を流入した時の断面図を示す。FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG. 2 is a sectional view when the sealing resin is poured.
回路基板１にバンプ（＝Ｊ Ｉ Ｃ２を１・゛Ｃボンテ
ィングした後、紫外線硬化と熱硬化併用型の接着剤４を
使用して、非接着側が接着側より幅小なる封止枠６ａを
回路基板に取付け、紫外線５を照射する。After bonding a bump (=J I C2) to the circuit board 1 at 1.5C, a sealing frame 6a with the non-adhesive side smaller in width than the adhesive side is formed using a combination of ultraviolet curing and thermosetting adhesive 4. Attach it to the circuit board and irradiate it with ultraviolet rays 5.
接着剤４は封止枠６ａの内外に多少はみ出し、更に封止
枠３ａＫ多少濡れ上がる。そのはみ出し部分４ａに紫外
線５が照射し、照射部分は数秒で硬化し、封止枠６は回
路基板１に仮固定される。この時封止枠６ａの上部が幅
小のため、紫外線５が確実に接着剤に照射される。The adhesive 4 somewhat protrudes into and out of the sealing frame 6a, and further wets the sealing frame 3aK to some extent. The protruding portion 4a is irradiated with ultraviolet rays 5, and the irradiated portion is cured in a few seconds, and the sealing frame 6 is temporarily fixed to the circuit board 1. At this time, since the width of the upper part of the sealing frame 6a is small, the adhesive is reliably irradiated with the ultraviolet rays 5.
而る後、第２図に示す如く、封止樹脂６を封止枠６内に
流入させ、加熱硬化（例えば従来と同様［１００℃、４
時間）させる。この加熱硬化時、接着剤４の紫外線未照
射部は、封止樹脂乙の加熱硬化時に同時に硬化され、回
路基板１と封止枠６は完全に接着される。After that, as shown in FIG.
time). During this heat curing, the unirradiated portion of the adhesive 4 is cured simultaneously with the heat curing of the sealing resin B, and the circuit board 1 and the sealing frame 6 are completely bonded.
第３図は本発明の第２実施例を示す断面図て、非接着剤
と接着剤の幅が同等なる封止枠６１）を使用した例であ
り、この場合接着剤４は封止枠６ａの内外に多少はみ出
１−ため、そこに紫外線５が照射するので仮接着がｉ」
能となる。後の説明は］二記と同じであるので省略する
。FIG. 3 is a sectional view showing a second embodiment of the present invention, and is an example in which a sealing frame 61) in which the non-adhesive and the adhesive have the same width is used. In this case, the adhesive 4 is used in the sealing frame 6a There is some protrusion inside and outside of the 1-, so ultraviolet rays 5 are irradiated there, so temporary adhesion is difficult.
Becomes Noh. The subsequent explanation is the same as in Section 2, so it will be omitted.
以上説明した如く、本発明によれば、仮接着の硬化時間
を極端に短くできるため同一装置で回路基板に対して月
止枠接着と封止樹脂流入が連続的に処理でき、且つ枠外
への樹脂流出が防止でき、信頼性の高し・低コストのＩ
Ｃ封止構造が実現できる。As explained above, according to the present invention, the curing time for temporary bonding can be extremely shortened, so that the same device can continuously process the bonding of the locking frame and the inflow of the sealing resin to the circuit board, and also prevent the inflow of the sealing resin from outside the frame. Highly reliable and low cost I that prevents resin leakage
A C-sealing structure can be realized.
第１図は、本発明の第１実施例で非接着側が接着側より
幅小な封止枠を使用した状態を示Ｊ−断［１１」図、第
２図は、第１図の状態に封止樹脂を流入し、ＩＣを封止
した状態を示す断面図であり、第３図は本発明の第２実
施例で、非接着側と接着側が同幅の封止枠を使用した状
態を示１−断面図でル）る。
１・・・・・回路基板、 ２・・・・パンダイ何ＩＣ
１６ａ、６１〕・・・・・封止枠、
４・・・紫外線硬化と熱硬化併用型接着剤、５・・・・
紫外線、
６ 封止樹脂。
第１図
第 ３１１Figure 1 shows the first embodiment of the present invention in which the non-adhesive side uses a sealing frame whose width is smaller than the adhesive side. FIG. 3 is a sectional view showing a state in which a sealing resin is poured and an IC is sealed. FIG. 3 shows a second embodiment of the present invention, in which a sealing frame with the same width on the non-adhesive side and the adhesive side is used. Figure 1 - Cross-sectional view. 1... Circuit board, 2... Pandai IC
16a, 61]...Sealing frame, 4...Ultraviolet curing and thermosetting adhesive, 5...
Ultraviolet rays, 6 sealing resin. Figure 1 No. 311
Claims (1)
実装構造において、前記回路基板と封止枠を紫外線硬化
と熱硬化併用型の接着剤を使用し、且つ封止枠の非接着
側は接着側に対して同等又は幅小なることを特徴とした
ＩＣの封止構造。In a mounting structure in which an IC is resin-sealed on a circuit board using a sealing IJ frame, the circuit board and the sealing frame are bonded together using a combination of ultraviolet curing and thermosetting adhesive, and An IC sealing structure characterized in that the width of the adhesive side is equal to or smaller than that of the adhesive side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8375583A JPS59208861A (en) | 1983-05-13 | 1983-05-13 | Sealing structure of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8375583A JPS59208861A (en) | 1983-05-13 | 1983-05-13 | Sealing structure of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59208861A true JPS59208861A (en) | 1984-11-27 |
Family
ID=13811358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8375583A Pending JPS59208861A (en) | 1983-05-13 | 1983-05-13 | Sealing structure of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208861A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304513A (en) * | 1987-07-16 | 1994-04-19 | Gao Gesellschaft Fur Automation Und Organisation Mbh | Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame |
| EP4195240A1 (en) * | 2021-12-13 | 2023-06-14 | Infineon Technologies AG | A method for fabricating a semiconductor device module by using a reactive tape and a semiconductor device module |
-
1983
- 1983-05-13 JP JP8375583A patent/JPS59208861A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304513A (en) * | 1987-07-16 | 1994-04-19 | Gao Gesellschaft Fur Automation Und Organisation Mbh | Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame |
| EP4195240A1 (en) * | 2021-12-13 | 2023-06-14 | Infineon Technologies AG | A method for fabricating a semiconductor device module by using a reactive tape and a semiconductor device module |
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