JPS59208782A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to simultaneously form a plurality of transistors which perform various kinds of functions by a method wherein, in the case of a circuit block containing three or more of transistor, the gates in the block are arranged in parallel. CONSTITUTION:A semiconductor integrated circuit device is generally divided into part A and part B, and the part A consists, for example, of a memory and the part B consists of a processor circuit located on the circumference. Different characteristics are required for the transistors used for the circuits of said part A and part B, and these transistors are formed in different sizes and also the pitches of the gates G are deviated. In this case, when all gates G are positioned in parallel, they are formed in the width T, and they are arranged in such a manner that the position occupied by the gates is included in the white and black pattern indicated by 2T, all gate patterns can be obtained by performing only one exposing process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to semiconductor devices, particularly semiconductor devices IB having a submicron rule of 1 micron or smaller,
It gives the plane configuration of f and its unidecimal method.

The present invention takes advantage of the characteristics of the semiconductor device described above and has a height of 1 t.
This invention relates to the configuration of a highly integrated # conductor integrated circuit having a mutual conductor Gm.

Structures of conventional examples and their problems Semiconductor devices have become increasingly dense in recent years, and semiconductor element dimensions are reaching submicron dimensions.1 To form this fine pattern, conventional exposure with ultraviolet rays is difficult. It is already considered to be at its limit, and recently far ultraviolet rays, X-rays,
Electron beam and ion beam exposure equipment are in the spotlight. However, the exposure equipment described in -1- is expensive, and exposure equipment using X-rays, 7-1i, laser beams, and ion beams, which are considered to be particularly effective for high quality exposure, is expensive. However, because the beam intensity was low and the exposure time was long, it was difficult to improve the quality of semiconductor devices.

Further, as a semiconductor device 11-1 having repeated A4 structures, there is a COD shown in FIG. FIG. 1 shows a perspective sectional view of a COD in the case of a 3'1 square pole, and the operation of the device is explained. COD essentially applies a MOS capacitor, and its structure is, for example, that an ion-implanted layer P+ for blocking the channel is formed on the surface of a P-type silicon substrate Q, and an oxide film is formed. 4 through the air (・υiP+,
P2. Form P3. The voltage of 1[゛ is P
When applied to l, the P-type majority carriers in silicon are divided by IJI, and a potential /I/2 is formed. The ion-implanted channel blocking layer restricts the spread of the ion-implanted channel well 2.

In the potential well 2 of 2, a small number of excited finite quantities are accumulated.?b, 1 P+, P
2.

When voltage is sequentially applied to P3, the potential Ugur becomes pj, P2. The silicon substrate 1 directly under P3 is moved, and the minority carriers are also transported along with the movement of this potential well. In the example of Figure 1, iHj
', the pitch L from P + to Pl is per cell, and is approximately six times as large as the C pitch L75=electron e<rh6 due to design.

1]'Y'iVc, CCD has 96 cono-t/L', 256: 9 more in a row, one #! This is limited to applications such as the delay element -r and the two-image element A, which exhibit high performance. In this case, when compared with 1-rangister,
In the case of 1-Ranshinuta, the functions that can be performed with the five type rods include nuinotink and signal amplification, but in COD, the functions that can be performed with (bow 1, three electric) j are minority carrier transport, and other functions. Other than the example shown in Figure 1, CCI does not have a two-phase type or CCI, which is considered to have the smallest shape.
4D structures etc. have been proposed. In the C4D structure, the effective barrier width of the electric current (minimum setting it = J'θ, I' of The length of is one cell length.

GC, D using MOS capacitors as shown in
In this case, whether an element is implemented that has a relationship of L-2kT (k = 1.2, 3...) between the minimum design dimension T and the length of 1 is limited to conveying a small number of gears directly under the rod, and its use is narrow. -Tsuba For BBDs that perform the same function as CODs, a junction FET in which the MOSFET's core is formed in an n-type epitaxial silicon layer and a structure that applies Schottky barrier transimec have been proposed, but 1 - Since the length of one cell forming a single cell cannot be limited by the minimum dimension, there is no relationship between the length of one cell and the minimum dimension as proposed by COD.

In the case of semiconductor memory, which is a typical example of a repetitive pattern, in order to minimize the pattern, the digits 1i'11, electric (!γ), and (5
7ii'i N:, 2kT of minimum line width T as in the present invention
Not twice selected. Moreover, in one element, MO
In the case of S, a pair of enhancement-type transistors and depth-reduction transistors are used together, but since the applied force of each 1 to 1 to 1-transinutor is different, the gate length and group l-width are different. and polysilicon wiring [1], etc., are inconsistent and standards are not standardized.
In the case of designing a planar groove/structure, the current state is that each transistor in the valley is installed one by one.

1. Transistors with large mutual conductance Gm, such as power transistors, have a labyrinth-like structure, as shown in Figure 2, and the cross-sectional shape is a repeating pattern of gates parallel to each other. .

G m CX aW/j is expressed by L, channel length, W + gate width, a2 height perpendicular to the PN junction surface 1, and in order to increase Gm, channel/L/
Make the length smaller, game) rl] W thicker, 171g.

As for the shape, as shown in FIG. 2, the comb-shaped electrodes of the source S and the 1-rufin D are interlocked alternately, and the extending gate 1-G is arranged between the source and the train.

The 21st line 1b shows a cross section along the dotted chain in FIG. 2a. Poly-Si 7 is formed as a gate by etching on the di-oxide film 6 formed on the wafer X5 containing the P4 impurity. A source S and a drain D are formed on the wafer 5 adjacent to this gate by diffusing impurities. 8 is a source and train electrode.

If we try to achieve higher Gm with the 1-lunge nug formed in this way, we can make the gate i] W better, channel)
It is necessary to make the V length shorter, but if you bend the wire as shown in Fig. 2, the bend will be 5°, .
(If the world concentrates or becomes more popular and becomes denser (・deni,
It has many problems and is not suitable for Amakawa.

In view of the problems of the conventional example, the present invention based on 1-1 of B.C. The purpose of the present invention is to provide a semiconductor integrated circuit device having a small size, which can perform many functions more efficiently using a small spacer.

Structure of the Invention The present invention is based on the minimum line width T of I.
) as the formation region of the transistor, and by repeating this formation region, we can have a plurality of mutually flat games 1-4! t: ii'i can be easily formed (in comparison, inexpensive laser holography-7,
'6! Exposure to i causes warts to be easily removed,
The present invention provides a conductor device with a material pattern 11. In addition, -], note 21 provides a transistor having a high Gm that takes advantage of the characteristics of the conductor device 1t.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a schematic diagram of a laser holography apparatus for exposing a semiconductor device according to the present invention.

11 is a laser generator, 12 is a mirror, 13 is a beam exnubander that combines a lens and a spatial filter, 14
is collimator lens, 15id: beam splinocou,
This is a semiconductor wafer coated with 16 lenses I-. As a laser, He-ICd laser it, 32
50 people, 4416 people), Ar ion laser (wavelength 4
579 people) can be used, and as a resist, AZ1350 (Zinoplay Winter 1), which is usually used in a bong type and is used for binding, or lij"fi, which is used because it has a photosensitive region for the oscillation wavelength of the laser mentioned in 1. The coherent I-light emitted from the laser is reflected by the mirror 12, and after expanding the beam by the heater 1 and expander 13,
After correcting the beam to a parallel beam using the collimator lens 14,
The beam is divided into two directions by the splitter 15 and reflected by the mirror 12 again, and the beams from the two directions are incident on the resist on the wafer 16.

When the wavelength of the laser is λ, the pinch of the grating is P, and the angle formed by the laser beams irradiating the resist on the wafer 16 from two directions is 2θ, the grating angle P can be expressed as P −λ /2s θ.

When the resist exposed in this way is developed, a black and white pattern of the line "1" at the end of P is obtained. By doing so, it is possible to form 9 crater ink pitches with a period of 2T on the wafer 16 with a size of about 0.2 to 2 .mu.m without using a mask.

Based on this resist pattern, if a pattern with a period of 2 mT is exposed twice and thrice and combined, the resulting pattern can be thinned out from the pattern with a period of 2 T/to obtain a repeating pattern that does not have a hit limit. . This is shown in Figure 4.

For example, in the pattern indicated by the 2T halo T, a resist pattern with a period of 2T is exposed, imaged, and re-exposed with a pattern with a period of 6T, which is three times that, resulting in a set of 3 resist patterns. Two of the lattice patterns are exposed, and after development, only one of the three pieces remains.When combined with other patterns in the same way, various patterns as shown in Figure 4 are created. is obtained.In addition, the minimum line rl]T
By masking with a pattern having +t+ which is an arbitrary integer multiple of the minimum line i]T and exposing it again from an arbitrary integer position as a unit, a pattern with a line width T can be formed on an arbitrary candy I￥f. I can do it.

FIG. 5 is an example of @1 to which the present invention is applied. Fifth
Figure a is a general view of the semiconductor integrated circuit device, and Figure 5 shows an enlarged view of a portion thereof. A semiconductor integrated circuit device is generally divided into a part A and a part B, as shown in FIG. 5a, where the part is, for example, a memory, and the part B is, for example, a peripheral processor circuit. This part person and part B
Since the transistors used in the circuit are required to have different characteristics, the individual transistors have different sizes and gate pitches, as shown in 5-1 and 7. In this case, l+ of all gates is T
If we arrange the gate 11 no 1 occupied by game 1 so that it is included in the black and white pattern to be beaten by 2T, we can obtain all the gate patterns by 11 and 1 of game 1.

J, the pattern of the peripheral part is made to have different gate dimensions by the conventional Hol-IJ Soxify method, and:
(: The first part of the man can also be removed by forming 11 patterns using the holographic method.

61st) dl, M obtained using parallel gates,
The connection diagram of one cell of the static RAM of the OS Mlaa and Kibo, obtained by Akira, is shown / ζ 1. In this diagram, the memory cell of 6 Shiko is shown, υ, Essentially, I. Landzisk Tl, T2 To negative (:
[+・5. / Instagram T5. This is a flip-flop consisting of T4. Its output transistor T5. It is connected to the 0 side and 1 side column lines via T6.

A row selection signal Xi is applied to Ts and Ts, and when a large number of such cells are connected to -. column lines, only one cell is selected. Although the above explanation is for the case of six elements, a four-element dynamic circuit composed of the four elements of the above-mentioned flip-flop and two capacitors can also be applied to one element.

FIG. 7 shows a circuit diagram of one cell of a three-element MOS guinamisocram obtained by applying the present invention and a wiring diagram of a gate arrangement obtained by the present invention V. In this example, the gates of the three transistors 'I'+, T2 and T3 are all parallel, and the gates of T+ and T2 are on the same straight line.
Second foot, write address line A+, read address line A
2. The four lines of the write data line D1 and the read data line D2 and the ground are connected to each cell surrounded by a dotted line. In this cell, transistor T2 and capacitor C store information. Since reading is performed by inverting the signal .gamma. through the transistor T3, an inverting amplifier B+4I is used for refreshing. By arranging these cells in a matrix pattern, g4c can be performed using the XY address.

Hereinafter, specific examples of an element SRAM and a three-element DRAM according to the present invention have been described, but these elements require a highly integrated arrangement of a large number of elements. In order to achieve high integration, the gate length and element formation rules were set to sub-micron dimensions, and in addition, the gate length and element formation rules were set to submicrons, and the gate lengths were formed for each element to be the same as before. , the disadvantages such as the proximity effect of the 'rH beam were severe, and in order to correct this, it was necessary to modify the drawing conditions, which took a considerable amount of time, and the nullput did not become large.

In the present invention, for example, all the gates in one cell, which is the smallest unit, are parallel, and in order to increase the area efficiency, at least two gates in one cell are arranged on the same straight line. There is. In fact, according to the exposure method using the holography method of the present invention, even higher throughput can be produced.

A specific embodiment of the semiconductor device according to the present invention is shown in FIG. 8, taking a P-well type CMOS as an example, and its process diagram is shown in FIGS. 9a, b, and c. This will be explained along the process chart shown in FIG.

First, 5ixN4 was applied to the semiconductor wiping plate 121 exhibiting n-type conduction.
A double membrane of crotch 1 8 and 5102 membrane 129 is formed on the entire surface,
Additional ion implantation to form the diffusion layer 122 of the P-well (
i/i) through a pattern of resins 1-130. At this time, the pattern pitch of resin 1- is set to the formation period T of the transistors to be formed from now on. In this case, the width of the Renst window is chosen to be 3T. After ion implantation, the substrate undergoes thermal diffusion to form a P-well exhibiting p-type conduction of the required depth (FIG. 9a).

Next, 5isNaB1 formed on the silicon substrate 121
A portion of the 29 and 5102 film 128 is etched to provide a window to allow the silicon substrate to oxidize, and a field oxide layer 123 is provided for each channel.

At this time, the repetition period of the field oxidized part is 6T, and the oxidized part is 3T (No. 9 l; Zlb)
.

Next, the Si3N4 film 129 and the 5i02 film 128 are removed, the polysilicon 125 is formed as a gate 1, and using this gate, the source and drain of the transistor (FIG. 9C) are formed by ion implantation. In the figure, a P well is formed and NMO3(N)K
However, the PMO5 portion (P) is implanted with resins 1 to 131. After that, PM, O3
After insulating the polysilicon 125 with an oxide film 126, an aluminum wiring 127 is provided and the 1-
Forms a lansimechium (Fig. 8). At this time, the polysilicon gate 1 is formed by lines 11]T with a period of 6T. This is 2 T/16 T shown in Figure 4.
It can be formed in the pattern shown in . In the aluminum wiring, as shown in FIG. 8, two parallel aluminum patterns each having a line width T are formed with a line rl and a line T in between, and the pitch thereof is indicated by 6T. This is shown in Figure 4 /ζ(2
T/16T)' pattern can be formed.

FIG. 10 shows an embodiment of the sen to which the present invention is applied, and the first
FIG. 0a is a general view of the semiconductor integrated circuit device, and FIG. 10 is an enlarged view of a portion thereof.

In this case, the design of the 1-range nut in the portion A' and the portion B' is different, and for example, a transistor with a large 1-length is required in the portion B'. As in the case of Fig. 5, if all gates are arranged so that the position occupied by the gate is included in the black and white pattern indicated by 2T, all gate patterns can be obtained by one exposure. be able to. At this time, the day 1-length is an integer multiple of T, and a black and white repeating pattern is used to make a must-throw,
By forming as many gates as possible, the pattern can be exposed all at once. Figure 10 is an example where the gate has three trees, and between the three-tree gates H is
The impurities are diffused in the same manner as those implanted into the source and drain to form a low resistance region, and the three gates 1- can be considered to be the same as one gate.

FIG. 11 shows an embodiment of the cage according to the present invention.

The characteristic of the Kijo example is that, in order to obtain a large 1-range nut of II + reciprocal contact Cm shown in Fig. 2, 1-range nutes having the same gate 1] are connected in parallel. . 21 is a semiconductor substrate, 22 is a gate oxide film, 23 is a poly 81 gate, 24 is an oxide film, 25 is a gate opening, and 26 is a shunt layer 4. At this time, the second
As shown in the figure, if there is one continuous gate in a labyrinth-like structure, there is a boundary between `` and E'' near the bending point of the gate 1-, but as in this example, polysilicon If an isolation layer 26 made of an oxide layer or the same type of impurity as the channel part is formed at both ends of the gate 23, and the source S and drain D are placed on both sides of the gate, a structure in which individual transistors are connected in parallel is formed. , the bending and concentration of the electric field at both ends of each gate 1- is eliminated, and a high Gm transistor can be provided by increasing the density.This transistor can be divided into gates 1 and 1; 26 is the area Ui
Make it into the shape shown in Figure 12 and connect the wiring fft'i.
You can simply.

Effects of the Invention As described above, the present invention arranges the gates in parallel in a circuit block including three or more transistors, and forms a quintile in a semiconductor integrated circuit by setting the gate [1] as a constant line "1". By doing this, it is possible to simultaneously form a 1-range nut that has the same functions as EJ, and furthermore, it is possible to provide a 1-range nut with high transconductance by connecting transistors with the same gate width in parallel. In fact, if the transistor according to the present invention is applied not only to holographic processing but also to device formation using electron beam exposure, there is no need to perform proximity effect correction using an electron beam, and it is no longer necessary to perform electron beam writing using a complicated program. disappears.

[Brief explanation of the drawing]

Figure 1 is a schematic cross-sectional perspective view of a conventional COD, Figure 2a,
b shows a plan view and a cross-sectional view taken along the line n-11' of a conventional Takamotomoku mutual conductor l-runnut, FIG. 3 shows an original diagram of a holographic device, and FIG. 4 shows an example of pattern formation according to the present invention. Figures 5a and 5b show the entire semiconductor device V1 according to an embodiment of the present invention (a technical diagram and a partially enlarged view, and Figure 6a).
, b is a circuit diagram of a 6-element memory cell using transistors constructed according to the present invention, and a specific element wiring diagram;
7a and 7b are circuit diagrams and specific element layout diagrams of a three-element memory cell using transistors constructed according to the present invention, FIG. 8 is a specific cross-sectional view of the element according to the present invention, and FIG.
Diagram a. b, c are explanatory diagrams of proscenes forming the element of Fig. 8;
FIGS. 10a and 10b show semiconductor devices i according to other embodiments of the present invention.
i:+ complete diagram 1 and enlarged view, Figure 11a,
b is another unspecified embodiment of the contactance transistor.
12 is a cross-sectional view of misfire 1, which is a modified version of the example shown in FIG. 11.
FIG. 6 is a schematic half-view of a transistor of an embodiment of νj; 11... Laser generator, 12... Mirror, 16...
...Semiconductor wafer coated with resin, S...source, D. drain, G...'l'-to, 21.
...'-1' Barrel substrate, 22... Gate oxide film, 2
3. Poly S1 gate, 26 minutes 14. 'J So. Name of representative Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3 Figure 4 Figure 5 Figure 10 Figure 11

Claims (1)

[Claims] (1) Several 1-lancinuta are formed in r summer, and “)1■
The region in which the transistor is formed is divided into a plurality of blocks, and the gates in the block are each made up of at least three transistors each operating independently, and the gates in the block are all formed in parallel, and an insulating film is formed on the semiconductor substrate. 1. A semiconductor device, wherein each of the channels formed in the semiconductor substrate directly under the gate formed through the gates has a current of XF ii. (2) 3 (ll'll) At least two of the gates in the block constituted by two transistors are formed in the same curve. Semiconductor device. (3) The semiconductor device according to claim 1, characterized in that the lengths of the gates of the 1-ranging terminals are approximately equal. (4) A black and white pattern with a period of 2T and the pattern KI
The semiconductor device fillLO(5) semiconductor according to claim 1, characterized in that a gate of a transistor is formed by a pattern formed by combining Q'1 and an integral multiple pattern. The leaf block of the device is characterized in that the main part and other blocks are formed as peripheral parts, and the length of the gate formed in the block in the peripheral part is different from the length of the gate a in the extra part. A semiconductor device according to claim 1. (6) The length of the semiconductor device in the peripheral portion is an integral multiple of the length of the main four portions! I-,
11. Semiconductor device 1171' according to claim 5,
. (7) A plurality of parallel gates are formed, and a channel is formed directly under the gates via the gate 1-oxide film, and the same type of impurity is diffused into each channel. At both ends of the channel, there are a source and a drain into which different types of impurities are diffused, and at the end of the gate, which extends approximately perpendicularly to the direction of the channel, there is a source and a drain with impurities of a different type diffused therein. A special feature is that a layer III is provided for the oxide film or the channel portion and the intercalated impurity diffused.
31' tax unit i'i:. (8) -'l! The conductor device is divided into 1" or multiple blocks, at least for forming the gate of the important part,
Using the exposure method of the Holocratic method, a pattern is formed by combining a black and white pattern with a period of 2T and a pattern that is an integer multiple of the pattern No. 11 to form a transistor game 1 constituting the semiconductor device of the block.
・A method for manufacturing a semiconductor device, characterized by forming a semiconductor device.