JP2007059680A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a layout surface area of a semiconductor device using a carbon nanotube (CNT) transistor. <P>SOLUTION: A semiconductor device comprises a first electrode 103, a second electrode 106 opposite to the first electrode with a first interlayer insulating film 104 disposed therebetween, a first CNT 108 passed between the first and second electrodes, a first gate insulating film 107 provided between the first interlayer insulating film 104 and the first CNT 108, and a first gate electrode 105 formed in the first interlayer insulating film 104 to be joined to the first gate insulating film 107. The semiconductor device further comprises a third electrode 116 opposite to the second electrode with a second interlayer insulating film 114 disposed therebetween; a second gate insulating film 117; a second CNT 118; and a second gate electrode 115 formed to have structures similar to the first gate insulating film, the first CNT, and the first gate electrode. The electrodes, the gate insulating films, the CNTs, and the gate electrodes form first and second field effect transistors 151 and 152 which are vertically positioned. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a field effect transistor using carbon nanotubes (CNT) and a method for manufacturing the same.

  The demand for miniaturization of conventional semiconductor devices using silicon has been increasing in recent years. However, in a field effect transistor using silicon (hereinafter referred to as an FET; Field Effect Transitor), a diffusion layer, a gate portion, and a separation portion are arranged in the horizontal direction on the surface of the silicon substrate, and such an FET structure. The density of integrated circuits in which are horizontally coupled is approaching its limit.

  Accordingly, vertical field effect transistor devices (vertical FET devices) in which FET structures are arranged in the vertical direction instead of FET structures in the horizontal direction have been developed.

  On the other hand, with the miniaturization of FETs using silicon, the gate insulating film made of a silicon oxide film has become as thin as possible (about 1.4 nm). This film thickness reaches the tunneling region directly, that is, the film thickness is thin enough to cause tunneling that directly conducts between the substrate and the gate electrode. For this reason, the gate leakage current of the FET increases, and the power consumption particularly in a stationary state is remarkably increased. For this reason, it is difficult to use a silicon oxide film as the gate insulating film.

  As a countermeasure against this, a high dielectric constant insulating film (for example, hafnium oxide) having a dielectric constant higher than that of a silicon oxide film is used as a gate insulating film, and by increasing the thickness of the gate insulating film, gate leakage current can be suppressed. Has been done. However, in the case of an FET using a high dielectric constant insulating film as a gate insulating film, it is known that switching characteristics deteriorate due to a decrease in carrier mobility compared to an FET using a silicon oxide film as a gate insulating film. It has been.

  In contrast, FETs that use carbon nanotubes (CNTs) to form channels have high transconductance, so there is little decrease in mobility even when combined with a gate dielectric film made of a high dielectric constant material, and switching characteristics deteriorate. It is possible to realize an FET that does not (see, for example, Non-Patent Document 1).

  A conventional vertical FET device using CNTs is disclosed in Patent Document 1. Hereinafter, the vertical FET device described in Patent Document 1 will be described with reference to the drawings.

  FIG. 10 shows an example of a semiconductor device 10 including a CMOS (Complimentary Metal Oxide Semiconductor) with CNTs.

  As shown in FIG. 10, the semiconductor device 10 is formed using a silicon substrate 11. A first interlayer insulating film 12 is formed on the silicon substrate 11, and a first electrode 13 is formed thereon. A second interlayer insulating film 14 is formed on the first interlayer insulating film 12 and the first electrode 13. Here, the second interlayer insulating film 14 has two openings on the first electrode 13.

  A first gate insulating film 15 and a second gate insulating film 16 are formed so as to cover the wall surfaces of the two openings of the second interlayer insulating film 14. Further, the first CNT portion 17 is formed so as to fill the opening via the first gate insulating film 15, and the second CNT is filled so as to fill the opening via the second gate insulating film. A CNT portion 18 is formed. A second electrode 19 is formed on the second interlayer insulating film 14 to cover the first gate insulating film 15 and the first CNT portion 17, and the second gate insulating film 16 and the second gate insulating film 16 are formed. A third electrode 20 that covers the CNT portion 18 is formed. A second electrode extraction electrode 21 and a third electrode extraction electrode 22 are formed on the second electrode 19 and the third electrode 20, respectively.

  Further, the first electrode 13 is sandwiched between the second electrode 19 and the third electrode 20 via the second interlayer insulating film 14 so as to be embedded in the second interlayer insulating film 14. A gate electrode 23 is formed. Here, the gate electrode 23 has a planar shape surrounding the first CNT portion 17 and the second CNT portion 18 via the first gate insulating film 15 and the second gate insulating film 16.

  A lead electrode 24 for the gate electrode is formed so as to be connected to the gate electrode 23 and embedded in the second interlayer insulating film 14. Furthermore, an extraction electrode 25 of the first electrode is formed so as to be connected to the first electrode 13 and embedded in the second interlayer insulating film 14.

  Here, the first CNT transistor 26 is formed by the first electrode 13, the second electrode 19, the first CNT portion 17, the first gate insulating film 15, and the gate electrode 23. A second CNT transistor 27 is formed by the first electrode 13, the third electrode 20, the second CNT portion 18, the second gate insulating film 16, and the gate electrode 23. That is, by applying a voltage to the gate electrode 23, the channel can be controlled in the first CNT portion 17 and the second CNT portion 18, and between the first electrode 13 and the second electrode 19 and The electrical connection between the first electrode 13 and the second electrode 20 can be switched on and off.

  Further, the first CNT transistor 26 has an N-type channel by ion implantation of K (potassium) into the first CNT portion 17. Further, the second CNT transistor 27 has a P-type channel because the second CNT portion 18 is not ion-implanted.

With the above configuration, a CMOS using CNTs is configured in the semiconductor device 10 illustrated in FIG.
JP 2004-165297 A SJ Wind Et Al, "Vertical Scalling Of Carbon Nanotube Field-Effect Transistors Using Top Gate Electrodes", Applied Physics Letters, P. 3817 Vol. 80, No. 20, 20 May 2002

  However, in the conventional CMOS using the CNTs, vertical CNT transistors, which are P-type and N-type transistors, are arranged in parallel in the semiconductor chip surface. In general, in a semiconductor device such as a memory, since the degree of integration directly reflects the cost, it is required to further reduce the area occupied by the memory cell by devising the layout.

  In view of the above, an object of the present invention is to provide a semiconductor device including an FET in which the occupation area of a memory cell is reduced and the flexibility of layout design is improved by vertically stacking vertical CNT transistors on a substrate, and The manufacturing method is provided.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first electrode formed on a substrate, a first interlayer insulating film formed on the first electrode, and a first interlayer insulating film. A first electrode formed on the second electrode formed opposite to the first electrode and a first interlayer insulating film between the first electrode and the second electrode; A carbon nanotube portion, a first gate insulating film interposed between the first interlayer insulating film and the first carbon nanotube portion, and a first interlayer insulating film are formed on the first gate insulating film. A first gate electrode in contact therewith, a second interlayer insulating film formed on the second electrode, and a third electrode formed on the second interlayer insulating film so as to face the second electrode; A second carbon nanotube portion formed so as to penetrate the second interlayer insulating film between the second electrode and the third electrode; A second gate insulating film interposed between the second interlayer insulating film and the second carbon nanotube portion; and a second gate formed in the second interlayer insulating film and in contact with the second gate insulating film A first field effect transistor is formed by the first electrode, the first gate insulating film, the first carbon nanotube portion, the first gate electrode, and the second electrode. The second electrode, the second gate insulating film, the second carbon nanotube portion, the second gate electrode, and the third electrode constitute a second field effect transistor.

  According to the semiconductor device of the present invention, since two carbon nanotube (CNT) transistors are vertically stacked, the layout area is smaller than that of a semiconductor device in which CNT transistors are arranged side by side in a conventional manner. A CMOS circuit or the like can be formed. This increases the number of wafers taken per wafer (the number of semiconductor devices to be manufactured), thereby reducing the manufacturing cost of the semiconductor device.

  Of the first field effect transistor and the second field effect transistor, one is a P-channel transistor and the other is an N-channel transistor, and the first field-effect transistor and the second field-effect transistor are Are connected in series to form an inverter, and a pair of inverters are preferably cross-coupled to provide a CMOS type memory cell.

  In this manner, in a static semiconductor memory device (SRAM) having CMOS memory cells, N-type CNT transistors and P-type CNT transistors are stacked in the vertical direction, so that it is conventional. Further, the layout area can be reduced as compared with the SRAM in which the N-type CNT transistor and the P-type CNT transistor are arranged in the lateral direction. For example, it is possible to form an SRAM with a layout area of about 70% compared to the conventional case, so that the number of wafers taken per wafer increases, and the manufacturing cost of the SRAM can be reduced.

  Moreover, it is preferable that an impurity is introduced into at least one of the first carbon nanotube portion and the second carbon nanotube portion.

  In this way, the first carbon nanotube portion and the second carbon nanotube portion can be arbitrarily formed into an N channel type and a P channel type. At the same time, the need to form a shielding mask for introducing impurities is reduced.

  That is, when both the N-type FET and the P-type FET are formed in the same layer parallel to the substrate as in the prior art, an impurity is introduced to form either the N-type or P-type FET. Therefore, it was necessary to form a shielding mask for preventing impurities from being introduced into the other FET.

  On the other hand, in the case of the semiconductor device of the present invention in which the P-type FET and the N-type FET are formed in separate layers, impurities are introduced into all of the FETs in one layer, so that a shielding mask is unnecessary. It has become.

  One of the first field-effect transistor and the second field-effect transistor is a P-channel transistor and the other is an N-channel transistor, and the first and second interlayer insulating films Of these, it is preferable that the film thickness of the N channel transistor is thicker than the other film thickness.

  Compared to a P-type CNT transistor, an N-type CNT transistor tends to cause a short channel effect. For this reason, by increasing the film thickness of the interlayer insulating film on which the N-type CNT transistor is formed, the gate length of the N-type CNT transistor can be increased, and the deterioration of the electrical characteristics due to the short channel effect is alleviated. be able to.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first electrode on a substrate, a first interlayer insulating film on the first electrode, and a first interlayer insulating film therein Forming a first gate electrode to be buried; forming a first opening in the first interlayer insulating film and the first gate electrode that exposes an upper surface of the first electrode; Forming a first gate insulating film covering a wall surface of the opening; forming a first carbon nanotube portion filling the first opening through the first gate insulating film; A step of forming a second electrode opposite to the first electrode on the interlayer insulating film, and a second interlayer insulating film and a second gate electrode embedded therein are formed on the second electrode. And exposing the upper surface of the second electrode to the second interlayer insulating film and the second gate electrode. Forming a second opening, forming a second gate insulating film covering the wall surface of the second opening, and filling the second opening through the second gate insulating film Forming a second carbon nanotube portion; and forming a third electrode opposite to the second electrode on the second interlayer insulating film.

  According to the method for manufacturing a semiconductor device of the present invention, the first field effect transistor is configured by the first electrode, the first gate insulating film, the first carbon nanotube portion, the first gate electrode, and the second electrode. In addition, the second field effect transistor is configured by the second electrode, the second gate insulating film, the second carbon nanotube portion, the second gate electrode, and the third electrode. A semiconductor device in which the effect transistor and the second field effect transistor are arranged so as to be stacked vertically on the substrate can be manufactured.

  Therefore, the layout area can be reduced as compared with the conventional semiconductor device in which the FETs are arranged side by side in a plane. For example, for a pair of stacked CNT transistors, a CMOS circuit can be formed by using one as a P-type CNT transistor and the other as an N-type CNT transistor.

  When the layout area is reduced in this way, the number of semiconductor devices that can be taken per wafer increases, which contributes to a reduction in manufacturing costs for individual semiconductor devices.

  Note that it is preferable to further include at least one of a step of introducing impurities into the first carbon nanotube portion and a step of introducing impurities into the second carbon nanotube portion.

  If it does in this way, an impurity can be introduce | transduced into at least one about the 1st and 2nd carbon nanotube part.

  In a conventional semiconductor device in which FETs are arranged in a plane, in order to form both P-type CNT transistors and N-type CNT transistors, it is necessary to introduce impurities into some CNTs. Therefore, in order to do so, a shielding mask is formed for the CNTs to which impurities are not introduced to prevent the introduction of impurities.

  On the other hand, according to the method for manufacturing a semiconductor device of the present invention, by introducing impurities into one of two vertically stacked CNT transistors, a P-type CNT transistor and an N-type transistor are introduced into the same semiconductor device. A CNT transistor can be formed. In order to do so, a shielding mask is not necessary, so that the process of forming and removing the shielding mask is not necessary, and the number of processes necessary for manufacturing a semiconductor device can be reduced. Note that P-type and N-type CNT transistors may be introduced by introducing P-type and N-type impurities into two vertically arranged CNT transistors.

  As described above, according to the present invention, it is possible to configure a CMOS circuit or the like having a layout area smaller than that of the conventional one by stacking and arranging the carbon nanotube transistors in the vertical direction. For this reason, the number of semiconductor devices to be taken per wafer increases, thereby realizing a reduction in the manufacturing cost of the semiconductor devices.

(First embodiment)
--Structure of semiconductor device--
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIGS. 1A and 1B show the configuration of the semiconductor device 100 of this embodiment including a CMOS circuit including a field effect transistor (FET) using carbon nanotubes (CNT). (A) is sectional drawing, FIG.1 (b) is a top view. However, both are schematic diagrams and do not represent the actual ratio of dimensions. Further, FIG. 1 (a) and FIG. 1 (b) are not the same scale. Furthermore, about FIG.1 (b), a one part component is abbreviate | omitted and the internal structure is shown.

  A semiconductor device 100 shown in FIGS. 1A and 1B is formed using a substrate 101 which is a silicon substrate, for example. A lowermost interlayer insulating film 102 is formed on the substrate 101, and a first electrode 103 is formed thereon. Further, a first interlayer insulating film lower layer 104 a is formed so as to cover the first electrode 103, a first gate electrode 105 is formed thereon, and further, a first gate electrode 105 is covered so as to cover the first gate electrode 105. One interlayer insulating film upper layer 104b is formed. As described above, the first gate electrode 105 is formed so as to be embedded in the first interlayer insulating film 104 including the first interlayer insulating film lower layer 104a and the first interlayer insulating film upper layer 104b.

  In addition, a second electrode 106 facing the first electrode is formed on the first interlayer insulating film 104. Further, a first opening is formed in the first interlayer insulating film 104 and the first gate electrode 105 so as to penetrate between the first electrode 103 and the second electrode 106, and the first opening is formed. A first gate insulating film 107 is formed on the wall surface of the opening. A first CNT portion 108 is formed inside the first gate insulating film 107 so as to fill the inside of the first opening via the first gate insulating film 107.

  Next, a second interlayer insulating film lower layer 114 a is formed on the first interlayer insulating film 104 so as to cover the second electrode 106. A second gate electrode 115 is formed on the second interlayer insulating film lower layer 114a, and further, a second interlayer insulating film upper layer 114b is formed thereon. As described above, the second gate electrode 115 is formed so as to be embedded in the second interlayer insulating film 114 including the second interlayer insulating film lower layer 114a and the second interlayer insulating film upper layer 114b.

  In addition, a third electrode 116 facing the second electrode is formed on the second interlayer insulating film 114. Further, a second opening is formed in the second interlayer insulating film 114 and the second gate electrode 115 so as to penetrate between the second electrode 113 and the third electrode 116, and the second opening is formed. A second gate insulating film 117 is formed on the wall surface of the opening. A second CNT portion 118 is formed inside the second gate insulating film 117 so as to fill the second opening through the second gate insulating film 117.

  In addition, a first extraction electrode 121 and a second extraction electrode 122 that respectively penetrate the interlayer insulating film and extract the potentials of the first electrode 103 and the second electrode 106 onto the second interlayer insulating film 114 are provided. Is formed.

  Further, the first gate extraction electrode 123a and the second gate that respectively penetrate the interlayer insulating film and extract the potentials of the first gate electrode 105 and the second gate electrode 115 onto the second interlayer insulating film 114, respectively. An extraction electrode 123 b is formed, and these are electrically connected to form the gate extraction electrode 123.

  As shown in FIG. 1B, the first gate electrode 105 planarly surrounds the first gate insulating film 107 and the first CNT portion 108. The second gate electrode 115 planarly surrounds the second gate insulating film 117 and the second CNT portion 118.

  Here, the first CNT transistor 151 is configured by the first electrode 103, the first gate electrode 105, the second electrode 106, the first gate insulating film 107, and the first CNT portion 108. That is, by applying a voltage to the first gate electrode 105, the channel in the first CNT unit 108 is controlled, and as a result, the electrical connection between the first electrode 103 and the second electrode 106. Is controlled.

  Similarly, the second CNT transistor 152 is configured by the second electrode 106, the second gate electrode 115, the third electrode 116, the second gate insulating film 117, and the second CNT portion 118. Yes. That is, by applying a voltage to the second gate electrode 115, the channel in the second CNT portion 118 is controlled, and as a result, the electrical connection between the second electrode 106 and the third electrode 116. Is controlled.

  As described above, the first CNT transistor 151 and the second CNT transistor 152 are arranged so as to be stacked vertically on the substrate 101. For this reason, the layout area is smaller than the case where the CNT transistors are arranged in a plane as in the conventional semiconductor device shown in FIG.

  Here, as an example of the dimensions, the diameter of the first CNT transistor 151 (in other words, the diameter of the first opening) is 80 nm, whereas the diameter of the first extraction electrode 121 is 50 nm. . Thus, the diameter of the CNT transistor is about 1.6 times larger than the diameter of the extraction electrode, and the layout area can be significantly reduced by arranging the CNT transistor vertically.

--Semiconductor device manufacturing method--
Next, a manufacturing method of the semiconductor device 100 of the present embodiment described above will be described with reference to the drawings.

  2A to 2D and FIGS. 3A to 3C are process cross-sectional views for explaining a manufacturing process of the semiconductor device 100. FIG.

First, as shown in FIG. 2A, a lowermost interlayer insulating film 102 made of SiO _{2 is formed} on a substrate 101, which is a silicon substrate, for example, by a CVD method (Chemical Vapor Deposition). To form. Next, a first electrode 103 made of doped polysilicon is formed with a thickness of 30 nm on the lowermost interlayer insulating film 102.

  Note that the first electrode 103 is formed as a pattern to be the source or drain of the CNT transistor in the present embodiment. Here, since the first electrode 103 is formed using doped polysilicon as a material, as described later, after depositing a metal on the doped polysilicon, silicide is formed and a CNT portion is formed. The silicide can be used as a seed (growth nucleus) layer.

Next, a first interlayer insulating film lower layer 104 a made of SiO ₂ is formed on the lowermost interlayer insulating film 102 by using a CVD method so as to cover the first electrode 103. Subsequently, the first interlayer insulating film lower layer 104a is planarized by a CMP method (Chemical Mechanical Polishing) so as to have a thickness of 30 nm from the upper surface of the first electrode 103.

  Next, the first gate electrode 105 is formed on the first interlayer insulating film lower layer 104a. For this purpose, for example, after a film made of an electrode material is formed to a thickness of 20 nm, a resist mask (not shown) is formed on the film and patterned by dry etching.

Subsequently, as shown in FIG. 2B, a first interlayer insulating film upper layer 104b made of SiO ₂ is formed on the first interlayer insulating film lower layer 104a so as to cover the first gate electrode 105. . As a result, the first gate electrode 105 is embedded in the first interlayer insulating film 104 composed of the first interlayer insulating film lower layer 104a and the first interlayer insulating film upper layer 104b. After that, the first interlayer insulating film upper layer 104b is planarized using a CMP method so as to cover the upper surface of the first gate electrode 105 with a film thickness of 30 nm.

  Next, a first opening 131 that penetrates the first interlayer insulating film 104 and the first gate electrode 105 and exposes part of the upper surface of the first electrode 103 is formed. The first opening 131 is formed with a diameter of 50 nm, and the depth is 80 nm which is the thickness of the first interlayer insulating film 104.

  Next, as shown in FIG. 2C, a first gate insulating film 107 is formed to a thickness of 5 nm on the wall surface of the first opening 131. For this purpose, for example, after a hafnium oxide film is formed on the entire inner surface of the first opening 131 by a CVD method, the hafnium oxide film on the bottom surface of the opening is removed by anisotropic dry etching, and the first The upper surface of the electrode 103 is exposed. Further, the hafnium oxide film formed over the first gate insulating film 104 is also removed.

  Next, as shown in FIG. 2D, the first CNT portion 108 is grown inside the first gate insulating film 107 so as to fill the first opening 131. At this time, the conditions are selected so that the first CNT portion 108 has a semiconductor property, and the first opening 131 is filled with a bundle of many CNTs.

  The first CNT portion 108 has a property of growing linearly from a seed layer (here, the bottom surface of the first opening 131, that is, the top surface of the first electrode 103). In other words, the first CNT portion 108 can be formed in the first opening 131 in a self-aligned manner, and therefore, a lithography process is unnecessary, and therefore alignment by a mask is also unnecessary.

  Prior to forming the first CNT portion 108, a seed layer (not shown) made of, for example, cobalt silicide is formed on the bottom surface of the first opening 131. For this, for example, cobalt is deposited only on the entire surface of the wafer or the bottom surface of the first opening 131 by sputtering, and then heat treatment is performed in a nitrogen atmosphere at 700 ° C. for one minute. By the heat treatment, the deposited cobalt reacts with the silicon forming the first electrode 103, and the silicide reaction proceeds. Thereafter, when the cobalt silicide formed on the portion other than the bottom surface of the first opening 131 is removed by etching, the seed layer is formed.

  Next, as shown in FIG. 3A, the second electrode 106 is formed on the first interlayer insulating film 104. This is formed so as to face the first electrode 103 and to be in contact with the first CNT portion 108 so as to cover the upper surface. Through the steps up to here, the first CNT transistor 151 including the first electrode 103, the gate electrode 105, the second electrode 106, the first gate insulating film 107, and the first CNT portion 108 is formed.

  Subsequently, the structure shown in FIG. 3B is formed by a process similar to that shown with reference to FIGS. That is, first, the second interlayer insulating film lower layer 114a, the second gate electrode 115, and the second interlayer insulating film upper layer 114b are formed in order. As a result, the second gate electrode 115 is formed so as to be embedded in the second interlayer insulating film 114 composed of the second interlayer insulating film lower layer 114a and the second interlayer insulating film upper layer 114b. Next, a second opening that exposes part of the upper surface of the second electrode 106 is formed in the second interlayer insulating film 114 and the second gate electrode 115, and the second opening is formed. A second gate insulating film 117 is formed on the wall surface. Further, a second CNT portion 118 is formed inside the second gate insulating film 117 so as to fill the second opening.

  Here, the second gate electrode 115 is 20 nm thick, the second interlayer insulating film lower layer 114 a is 35 nm from the upper surface of the second electrode 106, and the second interlayer insulating film upper layer 104 b is the upper surface of the second gate electrode 115. To 35 nm. As a result, the thickness of the second interlayer insulating film 114 is 90 nm, and the thickness of the second CNT portion 118 is also 90 nm.

  Next, K (potassium) ions are implanted into the entire surface of the wafer, thereby introducing K into the second CNT portion 118 to form an N-type channel. The ion implantation conditions at this time can be determined as follows, for example.

Since the thickness of the second CNT portion 118 is 90 nm, the projection range (Rp) may be set to 45 nm. For this purpose, the implantation energy was set to 40 keV by simulation (here, TRIM was used as a simulator, and the density of CNT was 2 g / cm ³ ). Further, the injection amount was determined to be 1 × 10 ¹³ atoms / cm ² from the actually created transistor switching characteristics. That is, the injection amount was experimentally determined by trial production.

  Here, when a plurality of CNT transistors are arranged in a plane in the same layer as in the prior art, when performing ion implantation of N-type impurities for forming an N-type channel CNT transistor, a P-type channel transistor is used. It was necessary to prevent ions from being implanted with respect to the CNT portion serving as the channel using a shielding mask. However, in the case of the semiconductor device 100, since the N-type channel CNT transistor and the P-type channel CNT transistor are formed in different layers, a shielding mask is unnecessary. For this reason, the number of processes for manufacturing a semiconductor device is reduced.

  In addition, the first CNT portion 108 was used for forming a P-type channel transistor as it was because the present embodiment showed P-type channel characteristics in an undoped state without introducing impurities. However, the characteristics of the additive-free CNT part may vary depending on the manufacturing method. Therefore, the P-type characteristics can be further stabilized by injecting F or Cl as necessary.

  Subsequently, as shown in FIG. 3C, a third electrode 116 is formed on the second interlayer insulating film 114. This is formed so as to face the second electrode 106 and to be in contact with the second CNT portion 118 so as to cover the upper surface. Through the steps up to here, the second CNT transistor 152 including the second electrode 106, the gate electrode 117, the third electrode 116, the second gate insulating film 117, and the second CNT portion 118 is formed.

  Further, the first electrode 103, the second electrode 106, the first gate electrode 105, and the second gate electrode 115 are electrically connected to each other, and the respective potentials are extracted onto the second interlayer insulating film 114. The extraction electrode 121, the second extraction electrode 122, the first gate extraction electrode 123a, and the second gate extraction electrode 123b are formed. Further, the first gate extraction electrode 123a and the second gate extraction electrode 123b are electrically connected to form the gate extraction electrode 123.

  The semiconductor device 100 of this embodiment is formed through the above steps.

  Here, in the semiconductor device 100 of the present invention, the thickness of the first CNT portion 108 (which is equal to the thickness of the first interlayer insulating film 104) is 80 nm, whereas the second CNT portion The thickness of 118 (which is equal to the thickness of the second interlayer insulating film 114) is 90 nm. This is because the N-type second CNT transistor 152 with the second CNT portion 118 as a channel is a P-type first CNT transistor with the first CNT portion 108 as a channel. This is because the short channel effect is likely to occur as compared with 151.

  In the case of a transistor using CNT, the short channel effect means that the distance between the source and drain provided at both ends of the CNT portion is shortened, so that the current between the source and drain is not applied to the gate electrode. Is a phenomenon that flows. When this phenomenon occurs, the original operation of the field effect transistor that controls the current between the source and the drain by applying the gate voltage is hindered.

  Such a short channel effect is more likely to occur in an N-type transistor than in a P-type transistor in a CNT transistor. Therefore, in the semiconductor device 100, the thickness of the N-type second CNT portion 118 is made larger than the thickness of the P-type first CNT portion 108, thereby reducing the influence of the short channel effect. is doing.

  Compared to the case where a plurality of CNT transistors are arranged in a plane on the same layer as in the prior art, the P-type channel CNT transistor and the N-type channel CNT transistor are formed in different layers as in the semiconductor device 100 and are arranged in the vertical direction. When arranged, the length of the channel (the thickness of the CNT portion) can be easily changed depending on the conductivity type.

  Next, FIG. 4 shows a circuit configured in the semiconductor device 100 described above.

  As shown in FIG. 4, the circuit configured in the semiconductor device 100 connects the gate lead-out wiring 123 by grounding the first lead electrode 121 and applying a power supply voltage of 5 V, for example, to the third electrode 116. A CMOS inverter circuit having the input and the second lead-out wiring 122 as an output is obtained.

  That is, voltage is applied to the gate lead-out wiring 123 that is electrically connected in common to the first gate electrode 105 included in the first CNT transistor 151 and the second gate electrode 115 included in the second CNT transistor 152. When “Hi (High)” is applied, the voltage “Lo (Low)” is output to the second lead wiring 122. On the other hand, when the voltage “Lo” is applied to the gate lead-out wiring 123, the voltage “Hi” is output from the second lead-out wiring 122.

  At this time, in the first CNT transistor 151, the first electrode 103 functions as a drain and the second electrode 106 functions as a source. In the second CNT transistor, the second electrode 106 functions as a source, and the third electrode 116 functions as a drain.

  Such a CMOS inverter circuit is used as a component of a semiconductor circuit, and an N-type channel CNT transistor and a P-type channel CNT transistor are stacked in a vertical direction, so that the layout area is reduced as compared with the conventional configuration. Yes.

(Second Embodiment)
Next, as a second embodiment, a static semiconductor memory device (SRAM) using a CNT transistor according to the present invention will be described with reference to the drawings.

  FIG. 5A shows a circuit diagram of a memory cell in an SRAM using a field effect transistor (FET). Since the memory cell having such a configuration is well known, detailed description is omitted. First, N-type channel transistors TN1 and TN2 are connected in series with P-type channel transistors TP1 and TP2, respectively, and two inverters are connected. It is configured. The two inverters are cross-coupled to form a flip-flop. Further, N-type channel transistors TN3 and TN4 are connected as a transfer gate for performing writing and reading between the flip flip and the bit lines BL and / BL.

  FIG. 5B is a diagram showing a conventional layout for realizing the memory cell shown in FIG. 5A on a substrate (not shown) by a MOS transistor. Hereinafter, the reference numerals correspond to the circuit diagram of FIG. 5A and the layout diagram of FIG.

  The memory cell is connected to the bit lines BL and / BL through contacts 301 and 302. The contacts 303 and 304 are each connected to a power supply line, and the contacts 303c and 304c are each connected to a ground line. Note that none of the bit lines BL and / BL, the power supply line, and the ground line are shown in FIG.

  Further, the contacts 303a, 305, and 303b are electrically connected by an upper layer wiring (the layout is not shown but is shown as an electrical connection 311). Similarly, the contacts 304a, 306, and 304b are also electrically connected by an upper layer wiring (not shown) (shown as an electrical connection 312).

  Further, as will be described later, the wirings 307 and 308 function as gate electrodes in four FETs constituting a flip-flop. Further, a word line 309 is formed.

  An impurity layer is formed in a region of the substrate between the contacts 303 and 303a, and the wiring 307 functions as a gate electrode, thereby forming TN1 which is one of FETs constituting a flip-flop. Similarly, the wiring 307 is used as a gate electrode, and TP1, which is one of FETs forming a flip-flop, is also formed in a region between the contacts 303c and 303b. Further, a transistor TN2 is formed between the contacts 304 and 304a using the wiring 308 as a gate electrode, and TP2 is formed between the contacts 304c and 304b.

  Further, an impurity layer is formed in a region of the substrate between the contacts 301 and 303a, and the word line 309 functions as a gate electrode, whereby the transistor TN3 is formed. Similarly, a transistor TN4 having the word line 309 as a gate electrode is formed between the contacts 302 and 304a.

  As described above, in the conventional SRAM realized by MOS transistors, the transistors TN1 and TP1, TN2 and TP2 each constitute an inverter circuit, and these two inverter circuits are cross-coupled to form a flip-flop. ing. The flip-flops are electrically connected to the bit lines BL and / BL by the transistors TN3 and TN4.

  In FIG. 5B, the boundary of the impurity layer necessary for forming one memory cell is shown as a rectangular range S1, and it is assumed that one memory cell occupies the inside as a layout area. Can do.

  In contrast to the conventional layout as described above, the present inventor has conceived of reducing the layout area by folding and overlapping a part of the layout. Specifically, with respect to the layout shown in FIG. 5B, it is folded along a straight line XX ′, and the portion including the contacts 303b and 304b is replaced with the portion including the contacts 303a and 304a (the straight line XX ′ The idea is to have a configuration in which they are stacked on a portion sandwiched between the straight line YY ′.

  When this is realized, the contacts 303c are stacked above 303, 303b is above 303a, 304b is above 304a, and 304c is above 304, stacked vertically on the substrate. Further, the transistor TP1 formed in the region between the contacts 303c and 303b is positioned above the transistor TN1 formed in the region between the contacts 303 and 303a. Similarly, the transistor TP2 is located above the transistor TN2.

  If such a layout can be realized, the layout area can be reduced. However, when a memory cell is configured using a MOS transistor having an impurity layer formed on a substrate as a constituent element as in the prior art, it is difficult to realize. That is, in order to fold the layout, it is necessary to form a transistor in a layer different from the substrate, but this cannot be realized by a normal MOS transistor.

  On the other hand, as described in detail in the first embodiment, since the FETs using CNTs according to the present invention are stacked in the vertical direction, a configuration in which the layout of FIG. 5B is bent can be realized. Is possible. An example of the semiconductor device will be described below.

  FIG. 6 shows a planar layout of a semiconductor device in which a configuration obtained by bending the layout of FIG. 5B is realized by using a vertical CNT transistor. In FIG. 6, straight lines X-X ′ and Y-Y ′ correspond to straight lines X-X ′ and Y-Y ′ in FIG. That is, the portion between the straight line X-X ′ and the straight line Y-Y ′ in FIG. 6 is a portion that has a layout that is stacked by folding. However, as will be described in detail below, FIG. 6 shows a configuration in which FIG. 5B is simply bent due to a difference between the MOS transistor and the CNT transistor and a change to reduce the area by reducing the wiring. Is different. Further, some components are not shown. Further, some of the wirings for constituting the flip-flop are only wirings 371 and 372 extending as shown by arrows in FIG. 6, and a specific shape is not shown. In addition, cross sections taken along lines XII-XII ′, XIII-XIII ′, and IX-IX ′ in FIG. 6 are shown in FIG. 7, FIG. 8, and FIG.

  It will be described below that the memory cell shown in the circuit diagram of FIG. 5A is realized in the semiconductor device of the present embodiment shown in FIGS.

  First, in the cross section shown in FIG. 7, a flip-flop composed of four CNT transistors is formed. That is, at the position A, the first N-type channel CNT transistor TN1 and the first P-type channel CNT transistor TP1 stacked on the TN1 are formed, and at the position B, TN2 that is the second N-type channel CNT transistor and TP2 that is the second P-type channel CNT transistor that are stacked on the TN2 are formed. Further, the intermediate layer electrode in which the gate electrode 361x of TP1 and the gate electrode 361y of TN1 are electrically connected by a wiring that does not appear in FIG. 7, and is shared by TN2 and TP2 and connected in series. It is electrically connected to 352b. This is shown as an electrical connection 371a (in FIG. 6, the state of extension of the gate electrodes 361x and 361y is indicated by the arrow 371). Similarly, the gate electrode 362x of TP2 and the gate electrode 362y of TN2 are electrically connected, and are further electrically connected to the middle layer electrode 352a shared by TN1 and TP1 and connected in series. Has been. This is shown as an electrical connection 372a (in FIG. 6, the state of extension of the gate electrodes 362x and 362y is indicated by the arrow 372).

  The configuration in which the N-type channel CNT transistor and the P-type channel CNT transistor are stacked vertically is the same configuration as that described in the first embodiment. Here, those corresponding to the first electrode, the second electrode, and the third electrode in the first embodiment are respectively the lower layer electrodes 351a and 351b, the middle layer electrodes 352a and 352b, and the upper layer electrode 353a in this embodiment. And 353b.

  Further, the lower layer electrode 351a, which is the other electrode of TN1, is connected to the contact 303, and is electrically connected to the power supply line through this. Similarly, the lower electrode 351b of TN2 is connected to the contact 304, and is electrically connected to the power supply line through this.

  In this way, the inverter composed of TN1 and TP1 and the inverter composed of TN2 and TP2 are cross-coupled to form a flip-flop.

  Here, at position A, a plurality of components corresponding to the components arranged horizontally in the conventional memory cell using the MOS transistor shown in FIG. 5B are stacked vertically. become. That is, one contact 303c connected to the ground and TP1, the other contact 303b connected to TP1, a contact 305 for cross-couple wiring, a wiring 307 functioning as a gate electrode common to TP1 and TN1, The wirings for performing the general connection 311 and the contacts corresponding to the one contact 303a connected to the TN1 are stacked. Similarly, at position B, a plurality of components (304c, 304b, 306, 308, wiring for making electrical connection 312 and 303a) in FIG. 5B are vertically stacked. Will be.

  Further, as shown in FIGS. 6 and 8, the middle layer electrode 352a shared by TN1 and TP1 extends toward the position C, and the lower layer electrodes 354a connected to the TN3 and TN3 formed at the position C and It is electrically connected to the bit line BL (see FIG. 5A) via the contact 301. Here, the word line 309 functions as the gate electrode of TN3. The middle layer electrode 352a also extends in the direction opposite to the position C, and is connected to the extended gate electrode 362y of TN2. As will be described later, since the gate electrode 362x and the gate electrode 362y of TP2 and TN2 are connected to each other, the middle layer electrode 352a is electrically connected to the gate electrode 362x and the gate electrode 362y. The electrical connection 372a in FIG. 7 is realized in this way.

  The gate electrodes 361x and 361y of TP1 and TN1 extend toward the position C, respectively, and are further connected to the middle layer electrode 352b shared by TP2 and TN2. The electrical connection 371a in FIG. 7 is realized in this way.

  Next, as shown in FIGS. 6 and 9, the middle layer electrode 352b shared by TN2 and TP2 extends toward the position D and is connected to the TN4 and TN4 formed at the position D. The bit line / BL (see FIG. 5A) is electrically connected through the contact 302. Here, the word line 309 functions as the gate electrode of TN4. Further, the gate electrodes 361x and 361y of TP1 and TN1 are extended and connected to the middle layer electrode 352b. As described above, this realizes the electrical connection 371a in FIG.

  The gate electrodes 362x and 362y of TP2 and TN2 extend in the opposite direction to the position D and are connected to each other. Thereafter, the gate electrode 362x is further extended and connected to the middle layer electrode 352a of TP1 and TN1. As described above, this realizes the electrical connection 372a in FIG.

  As described above, in the semiconductor device of this embodiment, a memory cell including a flip-flop configured using an N-type channel CNT transistor and a P-type channel CNT transistor arranged vertically is realized, and the storage device Function as.

  The description of the method of cross-coupled wiring is an example, and it is only necessary that electrical connection is realized, and the method is not limited to the described method.

  In the semiconductor device using the CNT transistor according to the present embodiment, the area of the rectangular range S2 indicating one memory cell is compared with the area of the range S1 in FIG. The occupied area is about 50%. This means that progress corresponding to two generations can be realized in the reduction of semiconductor devices.

  In the range S1 shown in FIG. 5B, the six transistors constituting the memory cell are separated by the separation region. On the other hand, in the case of the semiconductor device of the present embodiment whose planar layout is shown in FIG. 6, since the separation region is unnecessary, the occupied area is determined by the width of the electrodes and the distance between the electrodes. Here, the calculation was performed assuming that the electrode width is 100 nm and the distance between the electrodes is 10 nm.

  As described above, as shown in the two embodiments, a plurality of CNT transistors are stacked in the vertical direction (perpendicular to the substrate), and compared with the conventional case in which the CNT transistors are arranged only in the horizontal direction. The occupied area on the substrate can be reduced. As a result, the number of semiconductor devices that can be taken per wafer increases, and the manufacturing cost of the semiconductor device can be reduced.

  Further, when all the CNT transistors formed in one layer are P-type or N-type, and the P-type and N-type CNT transistors are formed in different layers, impurities for making the CNT transistor P-type or N-type It is not necessary to use a shielding mask for introduction. Thereby, a process can be simplified.

  In addition, for an N-type channel CNT transistor that tends to cause a short channel effect, the short channel effect is suppressed and the electrical characteristics are reduced by making the gate length longer (increasing the thickness of the CNT portion) than the P-type channel CNT transistor. Degradation can be mitigated. This is difficult with the conventional configuration in which P-type and N-type CNTs are arranged in the horizontal direction.

  In the above description, a two-layer structure in which two CNT transistors are stacked in the vertical direction has been described. However, a structure in which three or more CNT transistors are vertically arranged may be employed.

  The semiconductor device of the present invention can reduce the layout area by vertically arranging field effect transistors using carbon nanotubes, and is useful as a memory device or the like with reduced manufacturing costs.

1A and 1B are diagrams showing a field effect transistor according to a first embodiment of the present invention, where FIG. 1A is a cross-sectional view of the main part, and FIG. 1B is a plan view of the main part. It is. 2A to 2D are cross-sectional views illustrating manufacturing steps of the field effect transistor according to the first embodiment of the present invention. 3A to 3C are cross-sectional views illustrating manufacturing steps of the field effect transistor according to the first embodiment of the present invention. FIG. 4 is a circuit diagram showing an inverter realized in the field effect transistor according to the first embodiment of the present invention. FIG. 5A is a circuit diagram of a static semiconductor memory device, and FIG. 5B is a layout diagram for realizing the circuit of FIG. 5A with a conventional MOS transistor. FIG. 6 is a plan view of a semiconductor device according to the second embodiment of the present invention in which the static semiconductor memory device whose circuit diagram is shown in FIG. 7 is a cross-sectional view taken along the line XII-XII ′ of FIG. 8 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 9 is a cross-sectional view taken along the line IX-IX ′ of FIG. FIG. 10 is a diagram showing a CMOS structure using a conventional CNT transistor.

Explanation of symbols

100 Semiconductor device 101 Substrate 102 Lowermost interlayer insulating film 103 First electrode 104 First interlayer insulating film 104a, 104b First interlayer insulating film lower layer and first interlayer insulating film upper layer 105 First gate electrode 106 Second Gate electrode 107 first gate insulating film 108 first CNT (carbon nanotube) layer 114 second interlayer insulating film 114a, 114b second interlayer insulating film lower layer and second interlayer insulating film upper layer 115 second gate Electrode 116 Third electrode 117 Second gate insulating film 118 Second CNT portion 121 First extraction electrode 122 Second extraction electrode 123 Gate extraction electrodes 123a and 123b First gate extraction electrode and second gate extraction Electrode 131 First opening 151 First CNT transistor 152 Second CNT transistors 301 to 306, 303a c, 304a~c Contacts 307, 308 wiring 309 word lines (WL)
310, 311 Electrical connection 351a, 351b Lower layer electrode 352a, 352b Middle layer electrode 353a, 353b Upper layer electrode 354a, 354b Lower layer electrode 361x, 361y, 362x, 362y Gate electrode 371, 372 Wiring 371a, 372a Electrical connection TN1 to TN4, TP1 , TP2 CNT transistor

Claims (6)

A first electrode formed on a substrate;
A first interlayer insulating film formed on the first electrode;
A second electrode formed on the first interlayer insulating film so as to face the first electrode;
A first carbon nanotube portion formed so as to penetrate through the first interlayer insulating film between the first electrode and the second electrode;
A first gate insulating film interposed between the first interlayer insulating film and the first carbon nanotube portion;
A first gate electrode formed in the first interlayer insulating film and in contact with the first gate insulating film;
A second interlayer insulating film formed on the second electrode;
A third electrode formed on the second interlayer insulating film so as to face the second electrode;
A second carbon nanotube portion formed so as to penetrate through the second interlayer insulating film between the second electrode and the third electrode;
A second gate insulating film interposed between the second interlayer insulating film and the second carbon nanotube portion;
A second gate electrode formed in the second interlayer insulating film and in contact with the second gate insulating film;
The first electrode, the first gate insulating film, the first carbon nanotube portion, the first gate electrode, and the second electrode constitute a first field effect transistor,
A second field effect transistor is configured by the second electrode, the second gate insulating film, the second carbon nanotube portion, the second gate electrode, and the third electrode. A semiconductor device. In claim 1,
Of the first field effect transistor and the second field effect transistor, one is a P-channel transistor and the other is an N-channel transistor,
An inverter is configured by connecting the first field effect transistor and the second field effect transistor in series,
A semiconductor device comprising a CMOS memory cell configured by cross-coupled a pair of the inverters. In claim 1 or 2,
A semiconductor device, wherein an impurity is introduced into at least one of the first carbon nanotube portion and the second carbon nanotube portion. In any one of Claims 1-3,
Of the first field effect transistor and the second field effect transistor, one is a P-channel transistor and the other is an N-channel transistor,
Of the first interlayer insulating film and the second interlayer insulating film, a semiconductor film in which an N-channel transistor is formed is thicker than the other film thickness. Forming a first electrode on the substrate;
Forming a first interlayer insulating film and a first gate electrode embedded therein on the first electrode;
Forming a first opening in the first interlayer insulating film and the first gate electrode to expose an upper surface of the first electrode;
Forming a first gate insulating film covering a wall surface of the first opening;
Forming a first carbon nanotube portion that fills the first opening through the first gate insulating film;
Forming a second electrode opposite to the first electrode on the first interlayer insulating film;
Forming a second interlayer insulating film and a second gate electrode embedded therein on the second electrode;
Forming a second opening exposing the upper surface of the second electrode in the second interlayer insulating film and the second gate electrode;
Forming a second gate insulating film covering the wall surface of the second opening;
Forming a second carbon nanotube portion filling the inside of the second opening via the second gate insulating film;
Forming a third electrode opposite to the second electrode on the second interlayer insulating film. A method for manufacturing a semiconductor device, comprising: In claim 5,
A method of manufacturing a semiconductor device, further comprising at least one of a step of introducing impurities into the first carbon nanotube portion and a step of introducing impurities into the second carbon nanotube portion.

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