JPS59208764A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59208764A
JPS59208764A JP8330883A JP8330883A JPS59208764A JP S59208764 A JPS59208764 A JP S59208764A JP 8330883 A JP8330883 A JP 8330883A JP 8330883 A JP8330883 A JP 8330883A JP S59208764 A JPS59208764 A JP S59208764A
Authority
JP
Japan
Prior art keywords
substrate
wiring
semiconductor chip
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8330883A
Other languages
Japanese (ja)
Inventor
Shoji Takishima
滝島　昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP8330883A priority Critical patent/JPS59208764A/en
Publication of JPS59208764A publication Critical patent/JPS59208764A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the semiconductor device which can be handled easily by a method wherein the outer terminal, to be provided on an insulating resin substrate, is formed using a metal thin wiring of 40-50mum in thickness, and after a semiconductor chip has been mounted on the die pad of the substrate, the electrode terminal provided on the semiconductor chip is connected to the metal wiring using a wire, and the wiring is bent downward at the outer circumference of the substrate, thereby enabling to form the outer terminal in microscopic structure. CONSTITUTION:A prescribed aperture 13 is provided on the insulating resin substrate 8 consisting of epoxy, polyimide and the like, a die pad 11 is provided on the substrate 8 surrounded by said aperture 13, and a plurality of thin metal wirings 9 of approximately 40-50mum in thickness are coated outside the substrate 8 partially through the intermediary of the aperture 13. Then, a semiconductor chip 6 is adhered to the pad 11, and the electrode terminal provided on the semiconductor chip 6 is connected to the wiring 9 using a bonding wire. Subsequently, the outer end part of the wiring 9 is bent downward at the outer circumference of the substrate 8, and the chip 6 and the wire part are sealed using resin 7.

Description

【発明の詳細な説明】 本発明は、微細な外部端子を有する。樹脂封ＩＬ型パン
ケージ半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention has fine external terminals. The present invention relates to a resin-sealed IL-type pancage semiconductor device.

半導体装置のパッケージ方式の代表的なものとして、樹
脂制止型パッケージがある。これは、リード・フレーム
と呼ばれる基体に半導体チップケ接続し、熱硬化性樹脂
なもって低圧成形し、さらに基体の一部を切断し、各々
に分離した外部端子を形成し友ものである。第１図はり
一部・フレームの平面図で、図中１はダイ支持バー、２
はダイフラッグ、３は外部端子、４はガイド孔％５はリ
ード支持パーである。第２図は一部切り開いた完成し几
樹脂封止型パッケージ半導体装置の斜視図で、６はチッ
プ、７は封止り樹脂ケ表わす。A typical packaging method for semiconductor devices is a resin-sealed package. This involves connecting a semiconductor chip to a base called a lead frame, low-pressure molding with a thermosetting resin, and then cutting a portion of the base to form separate external terminals for each. Figure 1 is a plan view of a part of the beam/frame. In the figure, 1 is a die support bar, 2
5 is a die flag, 3 is an external terminal, 4 is a guide hole, and 5 is a lead support hole. FIG. 2 is a partially cutaway perspective view of the completed resin-sealed packaged semiconductor device, where 6 represents a chip and 7 represents a resin encapsulation.

近年の高密度実装の要求から、パッケージの小型化がは
かられ、Ｓ　ＯＰ　（Ｓｍａｌｌ　０ｕｔｌｉｎｅ　Ｐ
ａｃｋ−ａｇｅ　）と呼ばれる小型の樹脂封止型パッケ
ージなどが現われている。これに使用されるリード・フ
レームは板厚が１５０μｍで、外部端子の線幅は４３０
μｎ〕、ピッチは１．２７醪が一般的である。今後さら
にピンチがＯ，’６３＋ａ＋以下になると予想される。In recent years, demands for high-density packaging have led to miniaturization of packages, and SOP (Small Outline P)
Small resin-sealed packages called ack-age have appeared. The lead frame used for this has a board thickness of 150 μm, and the line width of the external terminal is 430 μm.
μn], and the pitch is generally 1.27 molar. It is expected that the pinch will become even lower than O,'63+a+ in the future.

しかし、リード・フレームの加工上線１川および線幅の
最小寸法は板厚と同等が限度である。し友がって、微細
化するには、板厚ケ小さくてろことが必要である。しか
るに、板厚７１００μｍ以下ＶＣすると、外部端子とし
て性能上不都合ケ生じる。However, due to the processing of the lead frame, the minimum dimensions of one line and line width are limited to the same as the plate thickness. In order to miniaturize the material, it is necessary to reduce the thickness of the plate. However, if the thickness of the VC is less than 7100 μm, there will be problems in terms of performance as an external terminal.

特に変形しＪＰｊいために、外部端子が不揃いになった
り、曲がったりして、検査や実装上著しく取扱いにくく
なる。したがって、リード・フレームの諸寸法乞微細化
してい（には、現状では限界がある。In particular, since it is deformed and hard, the external terminals may become uneven or bent, making it extremely difficult to handle in terms of inspection and mounting. Therefore, there are currently limits to the miniaturization of various dimensions of lead frames.

本発明の目的は、したがって、徽細な外部端子でありな
がら、取扱い容易な半導体装置ケ提供することである。Therefore, an object of the present invention is to provide a semiconductor device that is easy to handle despite having a thin external terminal.

上記目的ケ達成する１こめに、本発明による半導体装置
は、絶縁基板と、該基板上に設けられた金属薄膜からな
る外部端子と、上記基板に載置され１こ半導体チップと
、該チップ上の所定の部分を上記外部端子と電気的に接
続する電気接続とを含み。To achieve the above object, a semiconductor device according to the present invention includes an insulating substrate, an external terminal made of a metal thin film provided on the substrate, a semiconductor chip placed on the substrate, and a semiconductor chip disposed on the substrate. and an electrical connection for electrically connecting a predetermined portion of the external terminal to the external terminal.

上記チップおよび上記電気接続が絶縁樹脂で抜機されて
いること馨侠旨とする。It is important that the chip and the electrical connections are cut out using insulating resin.

以下に、図面を参照しながら、実施例を用いて本発明ン
一層詳卸］Ｋ説明するが、それらは例示にＪ／句ぎず、
本発明の枠を越えることなしにいろいろな変形や改良が
あり得ることは勿論である。The present invention will be explained in more detail below using examples with reference to the drawings;
Of course, various modifications and improvements can be made without going beyond the scope of the present invention.

第３図は本発明による半導体装置の製造工程途中におけ
る１０１而図、第４図および第５図は本発明による半導
体装置のそれぞれ断面図および平面図で、図中８（工絶
縁樹脂基本、９は金属配線、１０はボンディング・ワイ
ヤ、１１はグイパッド、１２は板状外部端子である。す
なわち、 本発明による半導体装置では、絶縁樹脂基体８上にチッ
プ６をつけるためのダイパラ＃″１１と、ボンディング
・ワイヤｌｏと接続され、外部端子３となる金属配線９
が金Ｍ薄膜で形成される。まＫ、絶縁樹脂基体８は低圧
成形時に佃脂ン流通させるための開孔部１３Ｔａ：備え
ている。この金属配線９は、公仰りフォトリングラフィ
技術により、金属薄膜をエツチング１−ることによって
形成されるもので、微細化が容易である。この金属配線
９の厚みは４０〜５０μｍで絶縁樹脂基体８の厚みはそ
の４〜５倍である。Ｐ３縁樹脂基体８は、例えは、エボ
キシャボリイεド糸樹脂で形成される。FIG. 3 is a 101 diagram showing the process of manufacturing a semiconductor device according to the present invention, and FIGS. 4 and 5 are a sectional view and a plan view, respectively, of the semiconductor device according to the present invention. 10 is a metal wiring, 10 is a bonding wire, 11 is a guide pad, and 12 is a plate-shaped external terminal.In other words, in the semiconductor device according to the present invention, a die plate #'' 11 for attaching the chip 6 on the insulating resin base 8; Metal wiring 9 connected to bonding wire lo and serving as external terminal 3
is formed of a gold M thin film. The insulating resin base 8 is provided with openings 13Ta for allowing the resin to flow during low-pressure molding. The metal wiring 9 is formed by etching a metal thin film using photolithography technology, and is easily miniaturized. The thickness of the metal wiring 9 is 40 to 50 μm, and the thickness of the insulating resin base 8 is 4 to 5 times that thickness. The P3 edge resin base 8 is made of, for example, epoxy resin.

不う６明による半導体装置では、昂４図に示されている
ように各々の外部端子は電気的に分離されているが、物
理的には絶縁樹脂基体上に形成されているので一体の板
状端子として存在している。In the semiconductor device by Akira Fuu6, the external terminals are electrically separated as shown in Figure 4, but physically they are formed on an insulating resin base, so they are integrated into one board. It exists as a terminal.

絶縁樹脂基体は金属配線に対して十分厚（、適度な硬度
と弾性をもっているので、板状端子は外部端子の性能乞
十分に満足しつつ、高密度のパックージとして成り立つ
。Since the insulating resin base has sufficient thickness (and appropriate hardness and elasticity) for the metal wiring, the plate-shaped terminal satisfies the performance of the external terminal and can be used as a high-density package.

第４図に７Ｊ＜す装置では、絶縁樹脂基体８０片面のみ
に金属配線９が形成されているが、第６図に４＜−「よ
うに両面に形成されることもできる。In the device shown in FIG. 4, the metal wiring 9 is formed only on one side of the insulating resin base 80, but it may be formed on both sides as shown in FIG. 6.

以」二説明し友通り、本考案によれば、外部端子の幅お
よびピッチを従来より微細にでき、しかもそれが絶縁樹
脂基体上に形＃：されているから、各各の９品子が不揃
いにならずに実装でき、筒密度実装が可能であるという
利点が得られる。As explained above, according to the present invention, the width and pitch of the external terminals can be made finer than before, and since they are formed on the insulating resin base, each of the nine items can be made finer than before. The advantages are that it can be mounted without any irregularities and that it is possible to perform cylinder density mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第１Ｍはリード−フレームの平面図、第２区は一部切り
開いた樹脂封止型パッケージ半導体装置の斜視図、第３
図＆工本発明による半導体装置の製造工程途中における
断面図、第４図および第５図＆λ本発明による半導体装
置のそれぞれ断面図および平面図、第６図を工水発明の
他の一つの実施の態様による半υネ体装匝の断面図であ
る。 ｔ・・・グイ支持バー、２・−・グイフラッグ、３・・
・外部端子、４・・ガイド孔、５・・・リード支持パー
、６・・・チップ、７・・・封止り樹脂、８・・・絶縁
樹脂基体、９・・・金属配線、１０・・・ボンディング
・ワイヤ、１１・・・グイパッド、１２・・・板状外部
端子、１３・・・開孔部。 特許出願人　　タラリオン株式会社 条Ｉ図 孝２図 年３図 年４図 年５図 参６図The 1st M is a plan view of the lead frame, the 2nd section is a partially cutaway perspective view of the resin-sealed packaged semiconductor device, and the 3rd section is a plan view of the lead frame.
FIGS. 4 and 5 are cross-sectional views and plan views, respectively, of the semiconductor device according to the present invention during the manufacturing process of the semiconductor device according to the present invention, and FIG. FIG. 3 is a cross-sectional view of a half-necked box according to an embodiment. t...Gui support bar, 2...Gui flag, 3...
- External terminal, 4... Guide hole, 5... Lead supporter, 6... Chip, 7... Sealing resin, 8... Insulating resin base, 9... Metal wiring, 10... - Bonding wire, 11... Guipad, 12... Plate-shaped external terminal, 13... Opening part. Patent applicant Tararion Co., Ltd. Article I Zuko 2 Figure 3 Figure 4 Figure 4 Figure 5 Reference 6

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板と、該基板上に設けられた金属薄膜からなる外
部端子と、上記基板に載置された半導体チップと、該チ
ップ上の所定の部分を上記外部端子と電気的に接続する
電気接続とを含み、上記チップおよび上記電気接続が絶
縁樹脂で板積されていることを％徴とする半導体装置。an insulating substrate, an external terminal made of a metal thin film provided on the substrate, a semiconductor chip placed on the substrate, and an electrical connection for electrically connecting a predetermined portion on the chip to the external terminal. A semiconductor device comprising: the chip and the electrical connection being laminated with an insulating resin.
JP8330883A 1983-05-12 1983-05-12 Semiconductor device Pending JPS59208764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8330883A JPS59208764A (en) 1983-05-12 1983-05-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8330883A JPS59208764A (en) 1983-05-12 1983-05-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59208764A true JPS59208764A (en) 1984-11-27

Family

ID=13798784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8330883A Pending JPS59208764A (en) 1983-05-12 1983-05-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59208764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device

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