JPS59207497A - Memory data compressing system - Google Patents

Abstract

PURPOSE:To shorten the time for decision of a relief line and at the same time to preserve all data by treating only the data that requires the analysis indeed as a compression data matrix. CONSTITUTION:The data of a fail memory 20 is delivered in response to the address given from a CPU21 or a generator 22 and given to line fail counters XLFC24 and YLFC25 respectively. Then the address is scanned again to read out the XLFC and YLFC data, and these data are compared with the redundant line numbers Ny and Nx by comparators 26 and 27 respectively. Then the comparator outputs 26a and 27a satisfying XLFC>Ny and YLFC>Nx are registered to the CPU21 as the relief fixed lines. At the same time, ''0'' is written to the corrresponding relief fixed addresses of XLFC24 and YLFC25 respectively. Then the addresses which are left within XLFC and YLFC as the data excluding ''0'' are given to the memory 20, and a compressed data matrix is formed only with the fail on the corresponding line.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory tester, and is particularly useful for determining whether or not the memory is defective in testing a memory that has a built-in redundant word or bit line to repair defective bits. This paper relates to a data compression method that is effective for performing necessary fail data analysis.

[Background of the invention]

Conventionally, a general semiconductor memory tester has a pattern generator 1 controlled by a timing signal output 6 of a timing generator 2, and a pattern generator 3 for a memory under test 3, as shown in the examples shown in FIGS. A comparator 4 that compares the output 11 with the expected value data 10 and outputs the result of determining whether the memory under test 3 is good or bad.
, and when the comparison result 12 from the comparator 4 is Fail, is it the same as the address given to the memory under test 3?
Alternatively, it is constituted by a fail memory 5 that writes fail information to the address of a fail memory configured to correspond, and after the test is completed, the internal medicine is taken out and the contents of the fail data are analyzed.

The pattern generator 1 provides the memory under test 3 hair trace 8 and the test pattern 9 as write data, and at the same time,
Expected value data 10 is output to the comparator 4 and control signal 7 is output to the timing generator 2.

The fail memory 5 is usually composed of a writable/extractable memory having the same or larger capacity than the memory under test 3, and has the same address 8 as the address given to the memory under test 3 from the pattern generator 1. is given.

On the other hand, improvements are being made to the manufacturing process in order to correct the decline in yield due to the Otani-based memory technology, but methods are also being used to increase the yield by devising the technology itself. I'm here. That is, even if there are some defective data in the memory, a method is being adopted in which the defect is replaced line by line using a built-in redundant bit line or warp IJ. FIG. 3 is a fail distribution diagram of the memory array 16 under test, and as a result of the test, the memories that failed from
This figure shows an example of saving circulation by replacing the book with two books on the low side (y). In this example, for fail cells that occur in the order from ■ to 0 indicated by an However, it may not be possible to recover depending on the distribution of fail occurrences and the number of fail cells. In this way, relief is determined based on the distribution and number of fail takes.
Judgment of whether or not it is e or not, and joint processing of the data 'J% for determining the salvage name, are performed by converting the take in the fail memory 5 shown in FIG.
Li13 is being read. However, the relief process is not just a take collection of test results, but is a special process that can be considered as part of the manufacturing process in which one memory is constructed, and requires a short process time. In the past, the method of treating the quantified fail memory take directly as a processing target for the CPU 13 resulted in too large a take amount.In addition, when looking at the fail distribution as a two-dimensional pattern on the fail memory 5, This is the processing content that the CPU 13 is weakest at.
It can be seen that reducing the processing time becomes extremely difficult.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art, and to be able to perform data analysis for repair in a short time in a memory tester that tests memory in which defective bits can be repaired using built-in redundant lines. The objective is to provide a take compression method that leaves only the data truly necessary for analysis.

[Overview of the invention]

The key point of the present invention is that the composition data of the two-dimensional file distribution must be determined by true computer analysis from among the test result data stored in the fail memory, rather than by scanning the entire data. Just compress the data
By performing computer processing on the IJ block, which is left as an IJ block and having a very small capacity compared to this disabled memory cell matrix, the relief line determination can be made in a short time.

[Embodiments of the invention]

In order to perform such data compression, the present invention performs the following 10 steps.
Two basic ideas are introduced.

(Li) Fins that fail or are lined up more than the number of redundant lines are confirmed as relief lines.In the past, when the number of confirmed relief lines exceeded the number of redundant lines, it was unconditionally determined that ζ was not salvageable.
When it is equal to or less than 9 liters of vinegar, there is a saving bow ability fr.

(2) The size of the data compression matrix σ), which is composed of computer-dismantled fail data for relief line determination, excluding the Yakusaki fixed edge, is defined by the number of unused (unallocated) redundant lines. size (x
1j! ll size: (NXXNY) 10Nx
, Y 911j size: (NXXNy) + Ny/However, Nx and Ny are X, yOll,! Number of unused redundant lines]
A larger crack is unconditionally determined to be unrepairable, and if it is equal to or smaller than that size, the oJfe for repair is
and can be subject to computer analysis.

The basic concepts of (1) and (2) above will be explained in detail below.

The cell array size of the actual slightly tested memory is 64x64.
(hit 4), 128
128 (16 people').

The addresses are large, such as 256 x 256 (64 bits), and the addresses at which failures occur also exhibit various distribution forms.

Figure 4 shows the above-mentioned basic information for this type of fail information (assuming that all empty areas other than "×-" in test memory fail map 17 are occupied by JE Hayabusa/Hito). Based on this idea, while maintaining the relative positional relationship between failed cells that have occurred in the memory circle under test, information on good cells that are unnecessary for waste phase processing and failures that are lined up more than the number of redundant cicadas is created. Da relief',, 1mf Udun (4th
The number of redundant lines Ny prepared in ``y'' in the figure is 2, so in order to compare 3 failures of the line with xiIlil address x4, use the line of
An example of the processing method of the data compression method is shown in which the data is removed in the form of 7 trixes, and the information that is required to be truly analyzed in the rescue judgment is left in the form of 7 trixes. It is an uninvented company-made fish.

The specific method of this pressure motion will be explained directly to the arrow.

XLFC and YLFC are line fail counters that count the number of failures on the valley, X side, and y theory lines. From this counter 1 shift, X4 is determined as a relief confirmed line as a line in which the number of redundant lines exceeds Nx = 2 and Ny = 2. Next, the number of failures obtained assuming that all the failures on this line of X4 are relieved is 1X
It is determined as LFc' and YLFσ.

In the end, the compressed data matrix 18 is obtained by extracting only the distribution of failures present in one or more lines in the XLFC and YLFC.

The computer uses Nx for this compressed data matrix.
= 1 line and Ny = 2 lines will determine all the relief lines, and in the example of Fig. 4, Xl, ys, y5 have already been determined
is determined as the relief line, and it is understood that it is better to perform analysis processing on only the 3×3 matrix 18.

Figure 5 shows the compressed data map I-IJ obtained in this way.
This is an example of a fail pattern showing that the size of the box 19 depends on the number of redundant lines. Nx = 2 as redundant line
At the end of the test for a memory under test having 2 books and Ny = 2, the size of the compression matrix that can take the maximum amount of fail data without causing the above-mentioned relief determination is up to 6
It becomes ×6. In this example, the relief lines are xt, x2. ys
, y6. This means that the fail is 2
The number of lines lined up is the number of redundant lines on the X side and y ti.
This is obtained from the fact that there can be valleys in ll.

As mentioned above, the matrix size obtained in this way is the maximum value of the X side size: (Nx xNy) +Nxy
The maximum value of side size 2 (NxxNy) is expressed by the number of redundant lines, such as 10NY. For example, in the example shown in Fig. 4, one line on the X side is used as the relief confirmation line, so the matrix size with the possibility of relief is on the X side: (lX2)+1=3
, y side: (1×2)+2=4. Now, it can be seen that the mar-IJ scale obtained here is 3×3, and there is a possibility of relief.

On the other hand, is there no remedy for failures that constitute a matrix size larger than the specified matrix size? lF
Either J' NQ or relief i will be confirmed, and neither of these can be used as data to be analyzed. For example, in Figure 5, ■ indicates that the line cannot be repaired, and ■ indicates that x2 is determined to be the line of relief.

FIG. 6 shows the data compression shown in FIG. 4 and the hardware configuration necessary for determining relief lines from the data compression matrix. In the past, the fail data input path from the memory under test to the fail memory,
It is configured as a data compression unit, so to speak, without all the hardware necessary for the Destination.

The data in the fail memory 20 is output in accordance with the address given from the CI'L 121 or the address generator 22 via the address bus 23, and is given to the line fail counters XLFC24 and YLFC25J. For line fail counters XLFC24 and YLFC25,
Fail memory 20 X.

The number of addresses on each address line of Y is counted and the total number for each line is stored. Of course, this counting may be performed at the same time as the fail data is written to the fail memory 20 during the eggplant 1f row.

After that, scan the address again and select XLFC, YL.
The FC data is output and compared with the redundant Hijy, Ny, and Nx by the comparators 26 and 27, and the X L
The comparator outputs (addresses) 26a and 27a where F C>Ny and Y L F C>Nx are registered as relief confirmation lines (addresses) in the CPU 21, and the line fail counters XLFC24 and/or YLFC2
For the relief confirmed address of 5,
'Write 17 entries as shown in Figure 4. Then, fix either the line fail counter XLFC or YLFC to the relief confirmed address (in the case of Figure 4, ') '-', scan the remaining addresses, For data other than 1 cell, 11 cells are subtracted (.This work is based on the fail distribution that can be obtained when all the fail cells on the relief confirmed address line are replaced with normal cells, as described above. This means that you have asked for data.

After performing the above operations with the help of CPU21,
Line fail counter X L l' C, YL k'
The remaining address as data other than "zero" in C is given to the fail memory 20, and only the failures on that line are collected to create a matrix (71), which is used as a compressed data matrix.

In this example, most of the data compression work is done by the CPU 21.
Although we have used the configuration with the help of /1-ware, it is also possible to configure it using only /1-ware. The address scan combines a counter and a clock, and the start address and end address are given from C)'U21 through the data bus 28, but when the address is given directly from the CPU 21, the address An output I control signal 21a is provided to an address generator 221.

In this way, by having the computer determine the relief line from the compressed data matrix, criteria for relief validity can be easily incorporated and changes can be made on the job.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained.

(Re) Only the data that is truly analyzed or necessary is used as pressure data.
Since it is treated as an IJ item, the time required for saving ωfMJ and determining it can be significantly shortened.

As an example, add bit memory to 256 redundant lines Nx=Ny
= If you save with 2 pieces, if there is no fixed line sword), the IJ box size is 6 x 6 and the amount of data to be handled is 36/256,000 kilos. /700
It will be reduced to 0. In the past, data transfer time to the CPU has been significantly shortened.

(2) The same effect can be obtained by installing small-scale hardware as shown in FIG. 6 in the conventional fail memory memory section.

(3) To avoid destroying fail memory data, all data must be saved.

(4) Registration of relief line and compressed data mat IJ
It is possible to judge whether or not it is salvageable at the stage of Kusu generation.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a general semiconductor memory tester, Figure 2 is a configuration diagram of a general tester used when testing multiple memories under test at the same time, and Figure 3 is an explanatory diagram of how redundant AI is used to repair defective bits. , Fig. 4 is a processing procedure diagram of the file data sharing method of the trial video memory according to the present invention, and the fifth example is an explanatory diagram of the judgment of the compressed data matrix when the compressed data matrix is changed by 1. FIG. 6 is a diagram showing one embodiment of the present invention. 17...Memory fail map under test 18.19...
・Compressed data matrix 20...fail distribution
21...CPU22...Address generator 23
...Address bus 24...x ``JIIJ line fail counter Nx - "°X side redundant gland number r' + y... y reception" redundant island number agent Patent attorney Ko Michiaki Figure 1 3rd figure: c (Catemno 4th figure 623 - Nbi = 2

Claims (1)

[Claims] In a semiconductor memory test device that uses redundant lines to repair defective bits, among the data in the storage device that stores test results, it is determined as an a+ relief line that contains more fail than the number of redundant lines, and this confirmed line The memory is characterized in that a fail distribution is generated from the remaining fail data excluding non-defective data while maintaining information on mutual relative positional relationships, and a relief line is determined based on this distribution. Data compression method.