JPS59204316A - Output suppressing circuit of logical circuit - Google Patents

Abstract

PURPOSE:To test a logical circuit accurately by grouping all external output terminals for respective unit outputs, and controlling external input terminals and verying a specific unit output of grouped output terminals. CONSTITUTION:The external output terminals 3-8 are grouped respectively and some set value is applied to external input terminals 1 and 2 for suppressing outputs to set all the terminals 3-8 to 0. Then, a test pattern is applied to an external input terminal of an LSI other than the terminals 1 and 2 and then the 1st input value to the terminals 1 and 2 is set to transmit signal variation by the test input pattern application to only one group of external output terminals, e.g. terminals 3 and 4. The 2nd input value is applied to the terminals 1 and 2 again and signal variation is transmitted to the terminal 5 from an internal circuit 23. Thus, the signal values of the terminals 3-8 are varied successively during a test to take the test of the logical circuit accurately without any influence of noises.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output suppression circuit for a logic circuit, which is incorporated in a logic circuit and is capable of suppressing output during testing of the logic circuit.

Conventionally, the implementation means for testing this type of logic circuit was to not provide an output suppression circuit, to prevent the outputs of the logic circuit from changing at the same time, and to change the input pattern to the logic circuit so that only some outputs changed at the same time. I was looking for a series. Now, when testing a logic circuit, for example an LSI (Large Scale Integrated Circuit), in order to test whether the manufactured LSI chip is free from failure and can be guaranteed to operate correctly, it is necessary to test the input terminals of the LSI. By applying a test pattern input from the LSI, observing the output from the output terminal of the LSI, and comparing this output value with the expected value, a tester can be used to test whether the LSI is operating correctly. Ta. By the way, during this test, noise may occur if the LSI's output occurs at multiple output terminals at the same time.For this reason, the correct LSI test cannot be performed. However, there was a possibility that it would be determined that there was a malfunction. therefore,
Conventional methods for testing LSI include:
A limit was set on the number of output changes so that the outputs of the LSI would not change at the same time, and tests were conducted to find a cover turn sequence that satisfied the limit.

Conventional implementation means for testing logic circuits are as described above, so when testing an LSI, for example, there are large restrictions on generating the input cover turn sequence, and it is difficult to easily generate the input cover turn sequence. I can't do it, and
Since the number of LSI outputs that change simultaneously is small, the input cover turn sequence becomes long, and the input cover turn generation time and test time are also long, and it is extremely difficult to obtain a high failure detection rate. there were.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in a logic circuit, all the plurality of external output terminals are grouped as unit outputs, and there is no need to suppress the output. The circuit includes a circuit that can change a specific unit output of the grouped external output terminals by controlling the external input terminal, and suppress the output so that other unit outputs do not change. It is an object of the present invention to provide an output suppression circuit for a logic circuit, which has a configuration in which the logic circuit can be accurately tested without being affected by noise.

An embodiment of the present invention will be described below with reference to the drawings. The figure is a configuration diagram showing an output suppressing circuit for a logic circuit according to an embodiment of the present invention. In the figure, 1.degree.2 is an external input terminal for suppressing output, 3 to 8 are external output terminals, and the external output terminals 3 and 4, 5, 6 to 8 are grouped, respectively.

9 to 13 are OR circuits, 14 to 16 are NOR circuits, 17 to 19 are output buffer circuits, 20 is a decoder, 21 and 22 are input buffer circuits, and 23 is an internal circuit, indicating the internal circuit of the LSI.

Next, the operation shown in FIG. 1 will be explained. First, by setting input values to external input terminals 1 and 2 to suppress output, the grouped external output terminals 3
Set all of ~8 to 0.

Next, a K test input cover turn is applied to external input terminals (not shown) of the LSI other than external input terminals 1 and 2 for suppressing output. After applying one series of test input cover patterns, by setting the first input value to external input terminals 1 and 2, the test input is applied to only one grouped external output terminal, for example, external output terminals 3 and 4. Conveys signal changes due to cover turn application. External input terminal 1 again,
2 is set to the next second input value, and the signal change from the internal circuit 23 is transmitted to the next one grouped external output terminal, for example, the external output terminal 5. In this way, the signal values of the grouped external output terminals 3 to 8 are sequentially changed. Thus, in the output suppression circuit of the logic circuit of the present invention, rather than controlling the external input terminals 1 and 2 for suppressing output, the signal values of the external output terminals 3 to 8 of the LSI are changed simultaneously. Instead, it is possible to sequentially change the unit outputs of the grouped external output terminals 3 to 8.

As described above, according to the output suppression circuit for a logic circuit of the present invention, by controlling the external input terminal provided in the logic circuit, for example, an LSI, to suppress the output, to 0 or 1,
Since the configuration is configured such that only the output of a specific grouped external output terminal is changed and the output of other external output terminals is not changed, there is no limit to the number of output changes when generating input patterns for LSI testing. It is extremely easy to generate tests, and the outputs of grouped external output terminals can be changed sequentially during testing, which eliminates noise problems and makes it possible to perform accurate tests. It has excellent effects.

[Brief explanation of the drawing]

The figure is a configuration diagram showing a logic circuit output suppression circuit according to an embodiment of the present invention. In the figure, 1, 21 external input terminals, 3-8... external output terminals, 9-13... OR circuit, 14-16...
NOR circuit, 17-19... Output sofa circuit, 2°... Decoder, 21.22... Input buffer circuit. Agent Masuo Oiwa

Claims (1)

[Claims] In a logic circuit, all of the plurality of external output terminals are grouped as unit outputs, and by controlling external input terminals for inhibiting output, the unit outputs of the grouped external output terminals are controlled. 1. An output suppression circuit for a logic circuit, comprising a circuit capable of suppressing an output so that a specific unit output of the circuit changes and other unit outputs do not change.