JPS59204254A - Manufacture of multilayer interconnection master slice integrated circuit - Google Patents
Manufacture of multilayer interconnection master slice integrated circuitInfo
- Publication number
- JPS59204254A JPS59204254A JP7905883A JP7905883A JPS59204254A JP S59204254 A JPS59204254 A JP S59204254A JP 7905883 A JP7905883 A JP 7905883A JP 7905883 A JP7905883 A JP 7905883A JP S59204254 A JPS59204254 A JP S59204254A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- chip
- wiring pattern
- pattern
- layer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 abstract description 21
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、多層配線マスクスライスＩＣの製造方法に関
するものである。、
ＬＳＩの製造方法の一つとして、プロセスの拡散工程終
了までのパターンを固定し、配線パターンを品種に応じ
て変更するというマスクスライス方式が知られている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring mask slice IC. As one of the LSI manufacturing methods, a mask slicing method is known in which the pattern is fixed until the end of the diffusion step of the process and the wiring pattern is changed depending on the product type.
一方ＬＳＩにおいては、複数の配線パターンを素子上に
縦横に錯綜させて形成する必要上、層間絶ｉ４層を介し
て複数のパターンを積層させると共に所定の箇所におい
てコンタクトホールな介して上下の配線パターンを電気
的に接続するという多層配線構造か採用されている。On the other hand, in LSI, it is necessary to form multiple wiring patterns in a complex manner vertically and horizontally on the device, so multiple patterns are stacked via an interlayer I4 layer, and upper and lower wiring patterns are connected through contact holes at predetermined locations. A multilayer wiring structure is used to electrically connect the two.
従来多層配線のマスタスライスＩＣを製造する場合、固
定パターンによる拡散工程か終了したのち、品種に応じ
た第１層パターン、第２層パターンを順次形成していた
ため、各層パターンごとにホトマスクを準備しなければ
ならないという煩雑さがあった。Conventionally, when manufacturing a master slice IC with multilayer wiring, after the diffusion process using a fixed pattern was completed, the first layer pattern and second layer pattern were sequentially formed depending on the product type, so a photomask was prepared for each layer pattern. There was the complexity of having to do so.
本発明は上記従来の問題点に鑑みてなされたものであり
、その目的は配線パターン用フォトマスクの個数を低減
させた多層配線用マスクスライスＩＣの製造方法を提供
することにある。The present invention has been made in view of the above conventional problems, and its object is to provide a method for manufacturing a mask slice IC for multilayer wiring in which the number of photomasks for wiring patterns is reduced.
上記目的を達成する本発明は、第１１醤配線パターンを
固定すると共に第２層以降の配線パターンを品種に応じ
て変更するように構成され、品種に応じて種々の第１層
配線パターン用ホトマスクン準備する手間が省かれる。The present invention, which achieves the above object, is configured to fix the 11th wiring pattern and change the wiring patterns in the second and subsequent layers depending on the product type, and to apply various photomasks for the first layer wiring pattern depending on the product type. It saves you time to prepare.
以下本発明の詳細を実施例によって説明する。The details of the present invention will be explained below with reference to Examples.
第１図乃至第２図は本発明の一実施例によってセットリ
セット何フリップ・フロップを製造する場合のテツゾ平
面図である。1 and 2 are plan views of a set-reset flip-flop manufactured according to an embodiment of the present invention.
まず第１図に示すように、適宜な公知手法によリシリコ
ンヂツプ１上にソース領域Ａ、ドレイン領域Ｂを形成し
た後、チップ全面をゲート酸化膜で被覆する。引続き、
ソース領域Ａとドレイン領域Ｂ内に電極形成用ホールを
開設した後ソース電極ａ、ドレイン電極す、ゲート電極
Ｃ及び固定の第１層配線パターンｄを形成する。最後に
、チップ全面に層間絶縁層を形成する。なお図示の便宜
上各電極と配線パターンの幅を無視すると共に、酸化膜
と絶縁層が透明であるがのように示している。First, as shown in FIG. 1, a source region A and a drain region B are formed on a silicon dip 1 by an appropriate known method, and then the entire surface of the chip is covered with a gate oxide film. Continuing,
After forming holes for forming electrodes in the source region A and drain region B, a source electrode a, a drain electrode S, a gate electrode C, and a fixed first layer wiring pattern d are formed. Finally, an interlayer insulating layer is formed over the entire surface of the chip. For convenience of illustration, the width of each electrode and wiring pattern is ignored, and the oxide film and insulating layer are shown as transparent.
次に第２図に示すように当該フリップ・フロップを構成
するのに必要なコンタクトホールｅを形成し、引続きこ
れらコンタクトホールを連ねるよ°子
うに第２層の配線バターダ）形成する。最後にチップ全
面をパッシベーション膜で被覆する。なお第２図に示さ
れているアルファベットは、通常のセットリセット付フ
リップ・フロップで使用される端子記号である。また上
述した箇々の製造工程は、すべて公知慣用のものである
から、これについての更に詳細な説明を要しないであろ
う。Next, as shown in FIG. 2, contact holes e necessary for constructing the flip-flop are formed, and then a second layer of wiring is formed so as to connect these contact holes. Finally, the entire surface of the chip is covered with a passivation film. Note that the alphabets shown in FIG. 2 are terminal symbols used in ordinary flip-flops with set/reset functions. Further, since all of the above-mentioned manufacturing steps are well known and commonly used, further detailed explanation thereof is not necessary.
以上２層配線構造の場合について本発明を例示したが、
３層以上の配線構造についても同様に本発明を適用でき
ることは明らかである。Although the present invention has been exemplified above for the case of a two-layer wiring structure,
It is clear that the present invention can be similarly applied to wiring structures having three or more layers.
以上説明したように、本発明は、第１層配線パターンを
固定すると共に第２層以降の配線パターンを品種に応じ
て変更する構成であるから、品種に応じて種々の第１層
配線パターン用ホトマスクを阜備する必要がなくなり、
ＩＣの設計時間と費用が大幅に低減される。また製造工
程を節減できるという利点もある。As explained above, the present invention has a configuration in which the first layer wiring pattern is fixed and the wiring patterns in the second and subsequent layers are changed according to the product type. There is no need to prepare a photomask,
IC design time and cost are significantly reduced. Another advantage is that the manufacturing process can be reduced.
第１図、第２図は本発明の一実施例を説明するためのチ
ップ平面図である。
Ａ・・・ソース領域、Ｂ・・・ドレイン領域、ａ・・・
ソース電極、ｂ・・・ドレイン電極、Ｃ・・・ゲート領
域、ｄ・・・第１層配線パターン、ｅ・・・コンタクト
ホール、ｆ・・・第２層配線パターン。
特許出願人 住友電気工業株式会社
代 理 人 弁理士玉畠久五部
第２図 ＪFIGS. 1 and 2 are chip plan views for explaining one embodiment of the present invention. A...source region, B...drain region, a...
Source electrode, b...drain electrode, C...gate region, d...first layer wiring pattern, e...contact hole, f...second layer wiring pattern. Patent applicant: Sumitomo Electric Industries, Ltd. Agent: Patent attorney Hisashi Tamabatake Figure 2 J
Claims (1)
て変更される第２層以降の配線パターンを順次形成する
ことを特徴とする多層配線マスクスライスＩＣの製造方
法。A method for manufacturing a multilayer wiring mask slice IC, characterized in that a fixed first layer wiring pattern is formed, and then second and subsequent layer wiring patterns that are changed depending on the product type are sequentially formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7905883A JPS59204254A (en) | 1983-05-06 | 1983-05-06 | Manufacture of multilayer interconnection master slice integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7905883A JPS59204254A (en) | 1983-05-06 | 1983-05-06 | Manufacture of multilayer interconnection master slice integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59204254A true JPS59204254A (en) | 1984-11-19 |
Family
ID=13679292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7905883A Pending JPS59204254A (en) | 1983-05-06 | 1983-05-06 | Manufacture of multilayer interconnection master slice integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59204254A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175241A (en) * | 1987-12-29 | 1989-07-11 | Fujitsu Ltd | Master slice of semiconductor device |
| EP0338817A2 (en) * | 1988-04-22 | 1989-10-25 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing the same using master slice approach |
| US5117277A (en) * | 1989-01-27 | 1992-05-26 | Hitachi, Ltd. | Semiconductor integrated circuit device with improved connection pattern of signal wirings |
-
1983
- 1983-05-06 JP JP7905883A patent/JPS59204254A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175241A (en) * | 1987-12-29 | 1989-07-11 | Fujitsu Ltd | Master slice of semiconductor device |
| EP0338817A2 (en) * | 1988-04-22 | 1989-10-25 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing the same using master slice approach |
| EP0650196A2 (en) * | 1988-04-22 | 1995-04-26 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing the same using master slice approach |
| EP0650196A3 (en) * | 1988-04-22 | 1995-05-10 | Fujitsu Ltd | |
| US5117277A (en) * | 1989-01-27 | 1992-05-26 | Hitachi, Ltd. | Semiconductor integrated circuit device with improved connection pattern of signal wirings |
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