JPS5920203B2 - signal conversion circuit - Google Patents

Description

Detailed Description of the Invention This invention relates to an insulated gate field effect transistor (hereinafter referred to as I
The present invention relates to a signal conversion circuit that converts a digital signal to an analog signal using a GFET (hereinafter referred to as GFET).

Conventional IGFETs have large threshold variations, so
Monolithic MO8ICs have rarely been used in linear integrated circuits, and circuits that convert digital signals into analog signals, which require particularly high precision, have rarely been constructed using monolithic MO8ICs.

An object of the present invention is to provide a signal conversion circuit that uses an IGFET and converts a digital signal into an analog signal with relatively high precision regardless of variations in the threshold value.

According to this invention, the first IGFET is made conductive by the first clock, and a predetermined amount of charge is charged in the capacitive element between the gate and drain of the second IGFET.

Next, the second IGFET is turned on by the second clock, and the charge in the capacitive element is transferred to the storage capacitive element.

The first clock and the second clock are repeated without overlapping each other, and the holding capacitive element is charged according to the number of clocks.

Utilizing this fact, if a number of clocks corresponding to the digital signal is supplied, an analog quantity corresponding to the digital signal can be obtained in the holding capacitor element.

The invention will now be described in detail with reference to the following drawings.

In each figure, for convenience of explanation, all transistors used are p-channel MOSFETs.

Figure 1 shows the case of converting an analog signal to a digital signal as a reference example of the present invention, where Ql is the input MO8FET.
The switch is shown in which the source of Ql is connected to analog signal input terminal 1, the gate is connected to terminal 20 to which sampling signal φS is applied, the drain is connected to the source of FET Q2 at node 2, and there is a connection between node 2 and ground. A holding capacitive element Cs is connected.

The gate of FET C2 is connected to the terminal 21 of the first clock φ1, and the drain is connected to the source of FET Qs at node 3.

A capacitive element C2 is connected between node 3 and terminal 21.

The gate of C3 is connected to the terminal 22 of the second clock φ2, the drain is connected to the source of the FET C4 at the node 4, and the capacitive element 03 is connected between the node 4 and the terminal 22.

The gate of C4 is connected to the terminal 21, and the drain is connected to the power supply terminal 23 of voltage Vd.

Node 4 also serves as an output terminal of the AD conversion circuit.

For convenience of explanation, each threshold value (Vt) of MO8FET Ql, C2, C3, and C4 is zero, and φ1. φ2:φS
The amplitude of is equal to Vd, and the capacitive element Cs is connected to the first clock φ
Vd - Vt from ground when 1 goes low four times
The size is such that it can be charged up to.

It is assumed that the sampling pulse φS becomes low level once when the second clock φ2 becomes low level five times or more.

It is assumed that the input to the terminal 10 is zero and the charges of the capacitive elements C8, C2 and C3 are all zero.

In this state, when the first clock φ1 is generated, the FET
Q becomes conductive, and the capacitive element C3 is charged to the voltage Vd.

Next, when C3 is made conductive by the second clock φ2, the charge in the capacitive element C3 is transferred to the capacitive element C2.

Furthermore, C2 and C4 are made conductive by the next first clock φ1,
The charge of the capacitive element C2 is transferred to the holding capacitive element Cs, and the capacitive element C3 is charged to Vd.

In this way, the voltage across each of capacitive elements C2 and C3 is Vd
Therefore, the potential of nodes 3 and 4 is -V
It changes between d and -2Vd depending on the clock.

Further, the holding capacitive element Cs is charged to Vd by charging four or more elements.

Next, consider a state in which input is provided from input terminal 1.

Now when the sampling pulse φS becomes low level t1
Ql becomes conductive, the potentials of input terminal 1 and node 2 become equal, and when φS returns to the ground level, the potential Vs of the input analog signal is sampled and held in capacitive element Cs.

When the next first clock φ1 is applied at time t2, C2
is transferred to C8, and in the same way, Cs is charged every time φ1 is applied, but when the voltage of Cs reaches Vd, it is no longer charged, and when this happens, the potentials of nodes 3 and 4 changes between -Vd and -Vd every φ1 and φ2.

The clocks φ1 and φ2 are shown in FIGS. 2A and 2H, the sampling pulse φS is shown in FIG. 2C, and the input terminal 10 is shown in the second diagram.

This input is actually made to fluctuate slower than the period of the sampling pulse φS.

The potentials at nodes 3 and 4 are shown in FIGS. 2F and 2G, respectively.

The number of clocks until the capacitive element C8 is charged to Vd changes depending on the level of the input signal held in the capacitive element Cs.

In FIG. 2, the voltage becomes Vd with two clocks φ1.

The number up to this Vd corresponds to the input analog value, which means that the input signal has been converted into a digital signal.

When the circuit shown in FIG. 1 is configured with a semiconductor integrated circuit, minority carriers are injected into the semiconductor substrate from the diffusion region of node 3, and the charge stored in the storage capacitor Cs is lost due to the parasitic transistor effect, resulting in malfunction. It may occur.

To prevent this, for example, as shown in FIG. 3, the capacitive element C2 between the node 3 and the terminal 21 in FIG. 1 may be connected between the node 3 and the ground.

Further, if the load capacitance connected to the output terminal 4 is negligible, the FET C2 and the capacitive element C2 may be omitted and the node 3 may be connected to the node 2.

If it is desired to further shift and extract the output signal, a packet brigade device may be connected.

When converting the circuit shown in FIG. 1 into a MOS/IC, the capacitance of the diffusion layer forming each node may become a problem.

That is, if the output part of FIG. 1 is shown in FIG. 4, the capacitance of the diffusion layer c
J is connected between node 4 and ground.

If the capacitance composed of the diffusion layer H atomized film-metal (MOS) is Cx, the capacitance CX between the node 4 and the terminal 22 is 03
Therefore, the voltage that can be extracted from node 4 as an output signal is proportional to CX/(CJ+CX).

Therefore, it is better to make the capacitance cJ of the diffusion layer smaller than the MO8O8 capacitance C.

For this purpose, for example, as shown in FIG. 5, an FFT Qs is formed using P-type diffusion layers 52a and 52b in an N-type silicon substrate 51 as sources and drains, and the drain diffusion layer 52b is extended to form a CX. Instead, this is made into a small region, its cJ is made small, and it is separated from this region 52b and formed on the wide P-type diffusion layer 53, and the MO8O8 capacitance of this diffusion layer 53, the insulating film 56, and the metal 54 is formed. C ratio C
3 and connect the gate 55 and region 53 of Qs to the terminal 22.
Connect to.

With this structure, the diffusion layer 53 of node 4 is connected to the drain 5 of C3.
CJ can be made significantly smaller than Cx since only the area for making contact with 2b can be made, and therefore distortion due to the variable capacitance characteristic of cJ and signal attenuation due to capacitance division can be reduced.

The characteristics of the A-D converter circuit in the reference example are affected by Vt and Cs/C3, so when configuring a comparator, Vt and C
In order to prevent variations in the manufacturing process of 8/C3 from being affected by the characteristics of the comparator, two A-D converter circuits are placed adjacent to each other, and one inputs a reference voltage and a signal to be compared to the other. By comparing the number of output pulses, it is possible to know the magnitude of the signal and the reference voltage, as well as the difference between them.

This method utilizes the fact that variations in transistors and capacitance within the same semiconductor universe are smaller than variations between lots.

If a highly accurate comparison is required that cannot ignore variations in Vt and capacity within the same Unibar, one A
-Using a D conversion circuit, store the relationship between the reference voltage and the number of output pulses in advance, and then compare the number of pulses when the signal to be compared next is input with the stored number of pulses, You can know the size and the difference between them.

The former method is less accurate but allows for faster comparisons, while the latter method is slower but allows for more accurate comparisons.

Next, a D-A conversion circuit for converting a digital signal to analog will be described as an embodiment of the present invention.

FIG. 6 shows an example of this, and the difference from FIG. 1 is that an FET Q is connected in parallel with the holding capacitive element Cs, and the node 2 is directly connected to the terminal 1.

There is also a FET between the node and the source of FET C2.
Qs is inserted, the terminal 24 is connected to its gate,
A digital signal is input to this terminal 24.

FIG. 7 shows the operating waveforms of FIG. 6, and FIGS. 7A and 7B show clock pulses φ1. φ2, FIG. 7C shows the reset pulse φS at the terminal 20, FIG. 7 shows the input digital signal from the terminal 24, and FIG. γE shows the voltage at the node 2, respectively.

Further, in FIG. 7, the waveform is shown with Vt set to zero.

Initially, it is assumed that terminal 1, that is, node 2, and the drain of FET C2C3 are charged to Vd-vt.

First, φS becomes a low level, and the charge stored in the capacitive element Cs is discharged to the ground level.

Next, after φS returns to the ground level, when φ1 becomes low level, the charge stored in capacitive element C2 is transferred to capacitive element C.
An attempt is made to charge the battery s, but since the terminal 24 is at ground level, that is, if there is no digital input, Q is non-conductive, so the battery Cs is not charged.

However, when the terminal 24 becomes low level due to digital input, FET C3 becomes conductive and the charge of capacitive element C2 is transferred to capacitive element C.
charged to s.

The digital signal at terminal 24 is synchronized with clock φ1.

In this way, the holding capacitive element Cs is charged with an electric charge corresponding to the number of digital signals.

If this Cs voltage is obtained from terminal 1, an analog output corresponding to the input digital signal can be obtained.

Note that due to the charge of capacitive element C2, capacitive element C8 becomes Vd-V.
Suppose that clock φ1 goes low level M times to charge up to t, the output waveform shown in Figure 2 is taken out as an output signal by a circuit with a threshold between ground and Vd0, and the number of output pulses is N. If so, A shown in Figure 1
In order to obtain the potential obtained by sampling the input voltage waveform in the -D conversion circuit at φS with the DA conversion circuit shown in FIG. 6, it is sufficient to apply M-N pulses to the input terminal 24.

Furthermore, when the circuit shown in FIG. 3 is used as the AD conversion circuit, the DA conversion circuit shown in FIG. 8 may be used.

As described above, in this invention, the capacitive element C3 is charged with a certain amount of charge from the constant potential of the terminal 23 at the clock φ1, and the charge of C3 is transferred to the holding capacitive element Cs at the clock φ2. The charge may not be transferred to Cs immediately, but may be relayed several steps in the middle.

You can control the number of clocks transferred to Cs using a digital signal to obtain an analog signal to Cs, or you can charge Cs with an analog signal and then use a digital signal depending on how many clocks are required for Cs to reach a predetermined potential. I can get a signal.

Note that the above embodiment is a p-channel enhancement type MO.
Although the circuit is constructed using S transistors, not only an n-channel enhancement type IGFET but also a depletion type can be used as long as it is back-biased to give enhancement type characteristics.

The structure shown in FIG. 5 can also be applied to the output of a bucket-brigate device.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an A-D conversion circuit as a reference example of the present invention, FIG. 2 is an operating voltage waveform diagram at each node of the circuit shown in FIG. A-D as a reference example
4 is a circuit diagram showing the stray capacitance of the diffusion layer, FIG. 5 is a cross-sectional view showing a structure that can reduce the stray capacitance of the diffusion layer, and FIG. 6 is a D according to an embodiment of the present invention. -A
FIG. 7 is a connection diagram showing a conversion path, FIG. 7 is an operating voltage waveform diagram of each terminal of the circuit shown in FIG. 6, and FIG. 8 is a connection diagram showing a D-A conversion circuit as another embodiment of the present invention. be. C3; first IGFET, C2; second IGFET, C
3: Capacitive element, C8: Holding capacitive element, 21: First clock terminal, 22: Second clock terminal, 23: Constant potential terminal.

Claims (1)

[Claims] 1 A first insulated gate field effect transistor (hereinafter referred to as IGFET) connected between a first node and a first power supply terminal and having a first clock applied to its gate; a second IGFET connected between the first node and to which a second clock synchronized with the first clock is applied without overlapping the first clock;
The first clock is applied to the first capacitive element connected between the gate of T and the first node, and the gate connected between the third node and the second node. Third IGFE
T, a second capacitive element connected between the gate of the third IGFET and the second node, and a fourth IGFET connected between the fourth node and the third node. , a holding capacitive element connected between the fourth node and a reference power supply terminal, applying a digital input signal synchronized with the first clock to the gate of the fourth IGFET, The fourth node is the output terminal, the first power supply terminal is connected to the first capacitive element in response to the first clock, and the first capacitive element is connected to the second capacitive element in response to the second clock. The method is characterized in that the storage capacitor is charged by moving an electric charge according to the same number of clocks as the number of clocks of the digital input signal, and an analog signal corresponding to the digital signal is obtained from this charging potential. Signal conversion circuit.