JPS5920197B2 - Sample/hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold circuit, and an object thereof is to provide a sample and hold circuit that can be easily integrated into an integrated circuit and has high accuracy.

FIG. 1 is a block diagram showing a conventional sample-and-hold circuit. To explain the operation using this diagram, an input signal input to an input signal terminal 101 is input to an input buffer amplifier 1.
02, the impedance is converted and the signal is supplied to the switching circuit 103.

On the other hand, the sampling pulse applied to the sampling pulse application terminal 104 is supplied to the drive circuit 105, drives the switching circuit 103, and samples the input signal. The sampled input signal is held by a capacitor 106, passes through a hold amplifier 107, and is output to an output terminal 1.
It is output on 08. The above is an explanation of the operation of the conventional sample-and-hold circuit.

In general, sample-and-hold circuits that require precision are
MOS transistors that do not require an input bias current are used at the input parts of the switching circuit 103 and the hold amplifier IOT.

The reason is that charge is supplied to the hold capacitor 106 during the sampling period from the input signal transmission system, so the switching circuit is required to have highly accurate switching characteristics as an analog switch, and the bias current of the switching element is This directly occurs as an error in the amount of charge stored in the hold capacitor 106. Also, on the other hand,
The input bias current of the hold amplifier IOT during the hold period also changes the amount of charge stored in the hold capacitor 106, causing an error. For this reason, MOS transistors that do not require input bias current are used. Therefore, most conventional sample-and-hold circuits integrated into circuits have a hybrid configuration.
However, the monolithic integration of the sample-and-hold circuit into a one-chip circuit requires a manufacturing process for high-frequency npn transistors, which are the main devices of the circuit, even though MOS transistors are necessary.

Therefore, the substrate of the MOS transistor is a P-channel MO
In S, it becomes an epitaxial layer, and in N-channel MOS, it becomes a base layer, and due to the non-uniformity of the concentration distribution, the variation in threshold voltage VT becomes large in both cases.

This variation in T occurs in the output as an offset voltage when the hold amplifier 107 is constituted by a MOS input operational amplifier, and its value is about several tens of mV. Further, a source follower of a MOS transistor can be used for the hold amplifier 107, but in this case, T itself appears in the output as an offset, and when used as a sample-and-hold circuit of an AD converter that requires high accuracy, the offset voltage is , the dynamic range of the AD converter is narrowed, resulting in the inability to satisfy the requirement for high accuracy. On the other hand, regarding the manufacturing process conditions for bipolar transistors, manufacturing a MOS transistor requires one additional step compared to the conventional bipolar process. That is, after the emitter diffusion is completed, it is necessary to remove the thick oxide film on the gate portion of the MOS transistor, and then perform heat treatment to form a new oxide film. For this reason, there is a possibility that the junction formation distance will be different for the Npn transistor that has already been manufactured, and desired characteristics will not be obtained. For these reasons, a compromise has to be made between the characteristics of the Npn transistor and the characteristics of the MOS transistor, and furthermore, the above-mentioned problem of the VT of the MOS transistor at the input section of the hold amplifier 107 can be solved by the single-chip monolithic sample-and-hold circuit. This was a difficult problem regarding integrated circuits. The present invention solves the above problems and
This eliminates the need to impose strict conditions on the VT of the OS transistor, and makes it possible to integrate bipolar transistors and MOS transistors into a single-chip monolithic circuit. The present invention will be explained below based on the embodiment shown in FIG.

To explain the operation using the drawings, the difference voltage between the input signal at the input terminal 201 and the output signal at the output terminal 223 is generated by the error detector 202 composed of a subtracter, etc., and this difference voltage is generated by the operational amplifier. 203, transistor 204, 20
5 and a resistor 206, the voltage is converted into a current, and the current is passed through transistors 207 and 208.

This current flows through transistors 216 and 217, which form a current mirror with transistors 207 and 208.
flows to Transistors 213 and 215 and 212 and 2
14 is ECL Emitsuta Cutup Logic (Emi
tterCOupledLOgic) constitutes a switch circuit, which performs switching using the DC bias determined by resistors 209 to 211 and a signal level-shifted from the sampling pulse from the sampling pulse input terminal 224 by the level shift circuits 218 and 219, and performs switching during the sampling period. In this case, transistors 213 and 214 are turned on, transistors 212 and 215 are cut off, and the hold capacitor 220 is charged and discharged.
During the hold period, transistors 213 and 2
14 cut off, transistors 212 and 215
is turned on so that the hold capacitor 220 is not charged or discharged. The MOS transistor 221 and the constant current source 222 constitute a source follower, which converts the voltage across the hold capacitor 220 into impedance and outputs it to the output terminal 223. Now, if the input signal is larger than the output signal during the sampling period, a positive differential voltage is generated at the output of the error detector 202, and the control means for controlling the amount of charge supplied to the hold capacitor 220 The transistor 205 of the voltage-to-current converter is cut off, and a current proportional to the differential voltage flows through the transistor 204.

Transistor 217 is thus cut off, and a current proportional to the differential voltage, ie, varying linearly with the differential voltage, flows through transistor 216, and this current charges hold capacitor 220 through transistor 214.
Therefore, the voltage across hold capacitor 220 increases, and the output signal at output terminal 223 also increases. Then,
The output of error detector 202 becomes smaller. In other words, this circuit is a circuit with negative feedback, and the above operation is repeated until the output signal matches the input signal. By the way, during the sampling period, if the input signal is smaller than the output signal, a negative differential voltage is generated at the output of the error detector 202, the transistor 204 of the voltage-to-current converter is cut off, and the transistor 205 is A current flows that is proportional to the differential voltage, that is, varies linearly in accordance with the differential pressure. Therefore, the transistor 216 is cut off, and a current proportional to the differential voltage flows through the transistor 217, and this current flows through the transistor 213 to the hold capacitor 2.
Discharge 20. Therefore, the voltage across hold capacitor 220 becomes small, and the output signal at output terminal 223 also becomes small. Therefore, the output of error detector 202 becomes small.
In this case as well, the above operation is repeated until the output signal matches the input signal. That is, the differential voltage output from the operational amplifier 203 is directly applied to the resistor 206;
Transistor 204 or 2 as a current determined by the value of
05, and this current flows through the hold capacitor 22.
Because it relies on charging and discharging at zero, the same hold capacitor 22
The current flowing through zero always changes linearly depending on the difference between the input signal and the output signal.

Therefore, the output terminal 223 outputs an output signal that completely matches the input signal. When the output signal matches the input signal, the output of the error detector 202 is zero volts, and the voltage-to-current converter transistors 204 and 205
Both are cut off.

Therefore, both transistors 216 and 217 are cut off, and the hold capacitor is no longer charged or discharged. During the hold period, the sampling pulse from the sampling pulse input terminal 224 cuts off the transistors 213 and 214 of the ECL switch circuit, turns on the transistors 212 and 215, and prevents the hold capacitor 220 from being charged or discharged. By doing this, the voltage during the sampling period is held.

Here, when analyzing how the output signal follows the input signal during the sampling period, the following equation is obtained.

Input signal is i, output signal is i.

, the value of the resistor 206 is R1, the capacitance of the hold capacitor 220 is the voltage between the gate and source of the ClMOS transistor is GS, then the current 1 flowing through the hold capacitor 220 is as follows.

When equations (1) and (2) are solved simultaneously, we get that, during the sampling period, the output signal follows the input signal even with the time constant of CR, and does not depend on the GS of the MOS transistor. I understand. As explained above, in the sample hold circuit of the present invention, the switching circuit is an ECL
Digital switches such as switch circuits can often be constructed from bipolar transistors. Furthermore, since there is no need to impose strict conditions on the T of the MOS transistor used in the input section of the hold amplifier, it is easy to integrate the MOS transistor with other bipolar elements on the same chip. In addition, since the control means controls the amount of charge supplied to the hold capacitor by changing linearly according to the magnitude of the output of the comparator,
Since the output signal completely follows the input signal linearly, a highly accurate sample-and-hold circuit can be obtained.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of a conventional sample-and-hold circuit;
The figure is a circuit configuration diagram showing an embodiment of the present invention. 201... Input terminal, 202... Error detector, 203... Operational amplifier, 204, 20
5,207,208,212-217...Transistor, 206,209-211...Resistor,
218, 219...Level shift circuit, 220
...Hold capacitor, 221...
-MOS transistor, 222...constant current source,
223...Output terminal, 224...Sampling pulse application terminal.

Claims (1)

[Claims] 1 a switch connected between a hold capacitor that accumulates charge corresponding to an input signal and a supply voltage source; an error detector that detects a potential difference between the input signal and an output signal based on the charge accumulated in the hold capacitor; a voltage-current conversion circuit that converts the voltage output of the error detector into a current output;
A sample-and-hold circuit comprising means for controlling the current supplied from the supply voltage source to the hold capacitor via the switch in accordance with the current output of the voltage-current conversion circuit.