JPS59201488A - Printed board - Google Patents

Printed board

Info

Publication number
JPS59201488A
JPS59201488A JP58076532A JP7653283A JPS59201488A JP S59201488 A JPS59201488 A JP S59201488A JP 58076532 A JP58076532 A JP 58076532A JP 7653283 A JP7653283 A JP 7653283A JP S59201488 A JPS59201488 A JP S59201488A
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
integrated circuit
terminal
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58076532A
Other languages
Japanese (ja)
Inventor
清 高木
勝之 濱田
黒沢 啓治
西原 幹雄
川俣 晴男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58076532A priority Critical patent/JPS59201488A/en
Publication of JPS59201488A publication Critical patent/JPS59201488A/en
Pending legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は多層プリント基板の層構成に係り、特に集積回
路素子を直接搭載するプリント基板に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the layer structure of a multilayer printed circuit board, and particularly to a printed circuit board on which integrated circuit elements are directly mounted.

(b)  技術の背景 プリント基板に集積回路素子を直接搭載して各種電子機
器の高密度実装化を図り、装置の小型化を行うべ〈従来
より各種の試みが成されているが、通當のプリント基板
の層構成では集積回路素子の直接搭載は信頼性の面から
不可能であった。
(b) Background of the technology It is necessary to directly mount integrated circuit elements on printed circuit boards to achieve high-density mounting of various electronic devices and to miniaturize the devices. The layer structure of the printed circuit board made it impossible to directly mount integrated circuit elements from a reliability standpoint.

第1図に従来の多層プリント基板の層構成を示す。エポ
キシ樹脂またはポリイミド樹脂の板1の片面に銅箔2を
張った複数枚のプリント基板a、エポキシ樹脂またはポ
リイミド樹脂の板1の両面に銅箔2を張った複数枚のプ
リント基板b、および絶縁層を兼ねた複数枚の接着材C
を積層して多層プリンI・基板3を構成している。各々
の銅箔2は回路構成上必要な部分のみを残して他の部分
は削除されており、各層の間はスルーボール鍍金で接続
されている。
FIG. 1 shows the layer structure of a conventional multilayer printed circuit board. A plurality of printed circuit boards a made of an epoxy resin or polyimide resin plate 1 covered with copper foil 2 on one side, a plurality of printed circuit boards b made of an epoxy resin or polyimide resin plate 1 covered with copper foil 2 on both sides, and insulation. Multiple sheets of adhesive C that also serve as layers
are laminated to form a multilayer print I/substrate 3. In each copper foil 2, only the parts necessary for the circuit configuration are left and the other parts are removed, and the layers are connected by through-ball plating.

第2図はプリント基板に集積回路素子を直接搭載した図
である。集積回路素子を搭載したセラミック基板4の裏
面には端子5があり、またプリント基板3表面の集積回
路素子を搭載する位置にも、セラミック基板4の裏面の
端子5に対応する端子6が配設されていて、端子5と端
子6は再溶融半田付は等によって接続されている。
FIG. 2 is a diagram in which an integrated circuit element is directly mounted on a printed circuit board. There are terminals 5 on the back surface of the ceramic substrate 4 on which the integrated circuit elements are mounted, and terminals 6 corresponding to the terminals 5 on the back surface of the ceramic substrate 4 are also arranged at the positions on the surface of the printed circuit board 3 where the integrated circuit elements are mounted. The terminals 5 and 6 are connected by remelting soldering or the like.

かかるプリント基板3に集積回路素子を直接搭載した場
合、プリント基板3と集積回路素子のセラミンク基板4
の熱膨張率の差が極めて大きい為に(プリント基板の熱
膨張率1.5X10  *ws/鶴℃、セラミック の
熱膨張率0.65 X 10−5w5 /顛℃)、稼働
時の熱ストレスにより集積回路孝子の端子5とプリント
基板の端子6の境界に、クランクが発生するという問題
があった。
When an integrated circuit element is directly mounted on such a printed circuit board 3, the printed circuit board 3 and the ceramic substrate 4 of the integrated circuit element are
Due to extremely large differences in thermal expansion coefficients (printed circuit board thermal expansion coefficient 1.5 x 10 * ws/Tsuru °C, ceramic thermal expansion coefficient 0.65 x 10-5 w5 / 2 °C), due to thermal stress during operation. There was a problem in that a crank occurred at the boundary between the terminal 5 of the integrated circuit Takako and the terminal 6 of the printed circuit board.

fd+  発明の目的 本発明の目的は多層プリント基板の層構成を改良し、集
積回路素子を直接搭載できるプリント基板を提供するこ
とにある。
fd+ OBJECTS OF THE INVENTION An object of the present invention is to improve the layer structure of a multilayer printed circuit board and to provide a printed circuit board on which integrated circuit elements can be directly mounted.

(el  発明の構成 そしてこの目的は多層プリント基板において、表面層と
して耐熱性を有し、且つ弾性係数の小さい樹脂の層を設
けることで達成している。
(el) Structure of the Invention This object is achieved by providing a layer of a resin having heat resistance and a small elastic modulus as a surface layer in a multilayer printed circuit board.

(fl  発明の実施例 稼働時の熱ストレスにより集積回路素子の端子5とプリ
ント基板の端子6の境界にクランクを発生させる応力σ
は、セラミックの熱膨張率をAs、弾性係数をEs、板
厚をTs、プリント基板の熱膨張率をAp、弾性係数を
E、、板厚をTp、温度差をTとすると次式で求めるこ
とが出来る。
(fl Stress σ that generates a crank at the boundary between the terminal 5 of the integrated circuit element and the terminal 6 of the printed circuit board due to thermal stress during operation of the embodiment of the invention
is obtained by the following formula, where As is the coefficient of thermal expansion of the ceramic, Es is the coefficient of elasticity, Ts is the plate thickness, Ap is the coefficient of thermal expansion of the printed circuit board, E is the coefficient of elasticity, is Tp is the plate thickness, and T is the temperature difference. I can do it.

σ=(八p−As)  T/  (1/Es +Ts/
Tp  −1/Ep)Ts=Tp、 A= (Ap  
As) T、とすればσ=A/ (1/Es+1 /E
p) 上式でEsがEpに比べて極めて大きければσは、はぼ
EpAに等しいと考えてよい。
σ=(8p-As) T/ (1/Es +Ts/
Tp -1/Ep) Ts=Tp, A= (Ap
As) T, then σ=A/ (1/Es+1/E
p) In the above equation, if Es is extremely larger than Ep, σ can be considered to be equal to EpA.

即ちプリント基板の表面層材料の熱膨張率が同じであっ
ても弾性係数が小さければ、集積回路素子の端子5とプ
リント基板の端子6の境界における応力σは小さくなり
、クランクの発生が減少する。
In other words, even if the coefficient of thermal expansion of the surface layer material of the printed circuit board is the same, if the elastic coefficient is small, the stress σ at the boundary between the terminal 5 of the integrated circuit element and the terminal 6 of the printed circuit board will be small, and the occurrence of cranks will be reduced. .

以下添付図により本発明の詳細な説明する。The present invention will be explained in detail below with reference to the accompanying drawings.

第3図は本発明の一実施例であり、第1図と同じ対象物
は同一符号で表す。多層プリント基板の中間層には従来
と同様に、エポキシ樹脂またはポリイミド樹脂の板1の
片面または両面に、銅箔2を張ったプリント基板aまた
はbを用いているが、表面層として、耐熱性を有し且つ
弾性係数の小さい樹脂、例えばポリブタジェン樹脂等の
板7の片面または両面に銅箔2を張ったプリント基板d
を用いている。
FIG. 3 shows one embodiment of the present invention, and the same objects as in FIG. 1 are denoted by the same symbols. The intermediate layer of a multilayer printed circuit board is a printed circuit board a or b made of an epoxy resin or polyimide resin plate 1 covered with copper foil 2 on one or both sides, as in the past. A printed circuit board d in which a copper foil 2 is pasted on one or both sides of a plate 7 made of a resin having a small elastic modulus, such as polybutadiene resin, etc.
is used.

ポリブタジェン樹脂の熱膨張率はエポキシ樹脂またはポ
リイミド樹脂と変わらないが、弾性係数はエポキシ樹脂
またはポリイミド樹脂の1/10になり (ポリブタジ
ェン樹脂の弾性係数は20X103kg / cl+、
エポキシ基材またはポリイミド基材の弾性係数は20 
X 104kg / cal )であり、セラミックの
弾性係数3(lxlO” kg/cn!に比べて1/1
50である。
The coefficient of thermal expansion of polybutadiene resin is the same as that of epoxy resin or polyimide resin, but the elastic modulus is 1/10 of that of epoxy resin or polyimide resin (the elastic modulus of polybutadiene resin is 20X103kg/cl+,
The elastic modulus of epoxy base material or polyimide base material is 20
x 104kg/cal), which is 1/1 compared to ceramic's elastic modulus of 3 (lxlO" kg/cn!)
It is 50.

したがって前述の数式から集積回路素子の端子5とプリ
ント基板の端子6の境界に発生する応力は、プリント基
板表面層の弾性係数にほぼ比例すると考えられ、従来の
プリント基板に比べてl/10に減少させることができ
る。
Therefore, from the above formula, it is thought that the stress generated at the boundary between the terminal 5 of the integrated circuit element and the terminal 6 of the printed circuit board is approximately proportional to the elastic modulus of the surface layer of the printed circuit board, and is 1/10 smaller than that of a conventional printed circuit board. can be reduced.

(gl  発明の効果 以上述べたように本発明によれば、稼働時の熱ストレス
により集積回路素子の端子とプリント基板の端子の境界
に、クランクを発生させる応力をほぼ1/10に減少さ
せ、集積回路素子を直接搭載できるプリント基板を提供
することができる。
Effects of the Invention As described above, according to the present invention, the stress that causes cranking at the boundary between the terminal of an integrated circuit element and the terminal of a printed circuit board due to thermal stress during operation can be reduced to approximately 1/10, It is possible to provide a printed circuit board on which integrated circuit elements can be directly mounted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図に従来の多層プリント基板の層構成、第2図にプ
リント基板に集積回路素子を直接搭載した図、第3図に
本発明の一実施例を示す。 図において1はエポキシ樹脂またはポリイミド樹脂の板
、2は銅箔、3は多層プリント基板、4はセラミック基
板、5.6は端子、7は耐熱性を有し且つ弾性係数の小
さい樹脂の板、aは板1の片面に銅箔2を張ったプリン
ト基板、bは板1の両面に銅箔2を張ったプリント基板
、Cは接着材、dは板7の片面または両面に銅箔2を張
ったプリント基板を示す。
FIG. 1 shows the layer structure of a conventional multilayer printed circuit board, FIG. 2 shows an integrated circuit element mounted directly on the printed circuit board, and FIG. 3 shows an embodiment of the present invention. In the figure, 1 is an epoxy resin or polyimide resin plate, 2 is a copper foil, 3 is a multilayer printed circuit board, 4 is a ceramic board, 5.6 is a terminal, 7 is a resin plate that is heat resistant and has a small elastic modulus, a is a printed circuit board with copper foil 2 stretched on one side of board 1, b is a printed circuit board with copper foil 2 stretched on both sides of board 1, C is an adhesive, and d is a printed circuit board with copper foil 2 stretched on one or both sides of board 7. The printed circuit board is shown.

Claims (1)

【特許請求の範囲】[Claims] 多層プリント基板において、表面層として耐熱性を有し
、且つ弾性係数の小さい樹脂の層を設けることを特徴と
するプリント基板。
A multilayer printed circuit board, characterized in that a layer of a resin having heat resistance and a small elastic modulus is provided as a surface layer.
JP58076532A 1983-04-30 1983-04-30 Printed board Pending JPS59201488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58076532A JPS59201488A (en) 1983-04-30 1983-04-30 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58076532A JPS59201488A (en) 1983-04-30 1983-04-30 Printed board

Publications (1)

Publication Number Publication Date
JPS59201488A true JPS59201488A (en) 1984-11-15

Family

ID=13607886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58076532A Pending JPS59201488A (en) 1983-04-30 1983-04-30 Printed board

Country Status (1)

Country Link
JP (1) JPS59201488A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319249A (en) * 1986-07-14 1988-01-27 松下電工株式会社 Metallic foil-lined laminated board
JPH02217240A (en) * 1989-02-20 1990-08-30 Matsushita Electric Works Ltd Surface mounting laminated sheet

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142670A (en) * 1977-05-19 1978-12-12 Fujitsu Ltd Method of producing multilayer printed board
JPS55126451A (en) * 1979-03-24 1980-09-30 Fujitsu Ltd Heat resisting property laminated board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142670A (en) * 1977-05-19 1978-12-12 Fujitsu Ltd Method of producing multilayer printed board
JPS55126451A (en) * 1979-03-24 1980-09-30 Fujitsu Ltd Heat resisting property laminated board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319249A (en) * 1986-07-14 1988-01-27 松下電工株式会社 Metallic foil-lined laminated board
JPH02217240A (en) * 1989-02-20 1990-08-30 Matsushita Electric Works Ltd Surface mounting laminated sheet

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