JPS59198022A - Ramp voltage generator - Google Patents
Ramp voltage generatorInfo
- Publication number
- JPS59198022A JPS59198022A JP7241183A JP7241183A JPS59198022A JP S59198022 A JPS59198022 A JP S59198022A JP 7241183 A JP7241183 A JP 7241183A JP 7241183 A JP7241183 A JP 7241183A JP S59198022 A JPS59198022 A JP S59198022A
- Authority
- JP
- Japan
- Prior art keywords
- current
- capacitor
- switch
- voltage
- slope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
- H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
この発明μ時間の軸過と共に上昇する傾斜重圧(鋸歯状
波電圧とも言うがこの明細書ではランプ(ramp )
電圧という)を発生するランプ電圧発生装置に関するも
のであろう
従来この袖の装置として第1図に示すものがあったっ図
において、Tlはトランジスタ、R1は抵抗、C1はコ
ンデンサ、FEB + kCBはそれぞれ電源、81ハ
スイツチ、VCはコンデンサC1の両端に発生するラン
プ電圧である。また、…源EF、B IECBの電圧値
をそれぞれEEB、EcBで示し、R1の抵抗値tR□
、 CIの静′屯谷量金C□とする。Detailed Description of the Invention This invention applies a ramp pressure (also referred to as a sawtooth wave voltage, but referred to as a ramp in this specification) that increases with the passage of μ time.
Conventionally, there was a device shown in Figure 1, which is related to a lamp voltage generator that generates a voltage (referred to as voltage). In the figure, Tl is a transistor, R1 is a resistor, C1 is a capacitor, and FEB + kCB are each The power supply, 81 switch, VC is the ramp voltage developed across capacitor C1. In addition, the voltage values of sources EF and B IECB are indicated by EEB and EcB, respectively, and the resistance value of R1 is tR□
, CI's static value is C□.
トランジスタTRIはペース接地であるためそのコレク
タ電流は負荷に関係なくほとんど一定値(すなわち電流
増幅率Xエミッタ′由流)に保たれるわすなわち電流増
幅率をαとすれば、スイッチS1を開いた後のコレクタ
電#L1−αEKI3/R□ であるように直線的に上
昇しE。Bに達するとi=0となってVcはほぼECB
の値に保たれる。第2図は時間tとVcとの関係を示
す図である。Since the transistor TRI is grounded, its collector current is kept at an almost constant value regardless of the load (i.e., current amplification factor E rises linearly as the later collector voltage #L1-αEKI3/R□. When B is reached, i=0 and Vc is almost ECB
is kept at the value of FIG. 2 is a diagram showing the relationship between time t and Vc.
式(1)から明らかなようにランプ電圧VCの傾斜はα
r EEB + C1+ Rtの値によって定められ、
この傾斜を微細に調整するためにはE[B r C1p
ktx等の値會微細に調整することが必散であるが、
これらの値を広帥囲yCわたって微細にかつ正確に調整
するには複雑な調整回路ケ必要とするという欠点があっ
た。As is clear from equation (1), the slope of the lamp voltage VC is α
determined by the value of r EEB + C1 + Rt,
In order to finely adjust this slope, E[B r C1p
Although it is necessary to finely adjust the value of ktx etc.,
There is a drawback that a complicated adjustment circuit is required to finely and accurately adjust these values over a wide range yC.
プラントのプロセス制#紫行う計算機やシーケンサから
プラント側へ出力するランプ電圧等においては、その傾
斜が微細にかつ正確に調整芒れていることが要求される
場合があり、従来の装置ではこの快求を満足することが
困難でめるという欠点があったっ
この発明は上記のような電流出力型のテイジタルアナロ
グ変換器(以下DACと略記する〕の出力Φ流を用いて
コンデンサを充電することにより、正確な値の傾斜を容
易に設定することのできるランプ電圧発生装置を提供す
ることを目的としている。There are cases where the slope of the lamp voltage output from a computer or sequencer to the plant is required to be finely and accurately adjusted, and conventional equipment cannot achieve this level of comfort. However, this invention has the drawback that it is difficult to satisfy the above-mentioned current output type digital analog converter (hereinafter abbreviated as DAC) to charge a capacitor using the output Φ current. Accordingly, it is an object of the present invention to provide a lamp voltage generator that can easily set an accurate slope value.
以下この発明の実施例について説明するっ第3図はこの
発明の一実施例を示すブロック図で、第1図と同一符号
は同−又は相当部分を示し、SRIはランプ出力電圧の
傾斜を数値で設定するディジタルスイッチ、CPlは制
御処理部、υB1はデータバス、DAIは電流出力型D
AC、AIは増幅器、S2は制御処理部CPIに起動信
号を与えるスイッチ、RPI 、 RP2はそれぞれプ
ルアップ抵抗でちる。An embodiment of the present invention will be described below. Fig. 3 is a block diagram showing an embodiment of the present invention. The same reference numerals as in Fig. 1 indicate the same or corresponding parts, and SRI indicates the slope of the lamp output voltage numerically. CPl is the control processing unit, υB1 is the data bus, DAI is the current output type D
AC and AI are amplifiers, S2 is a switch that provides a start signal to the control processing unit CPI, and RPI and RP2 are pull-up resistors, respectively.
1)ACの動作についてはよく知られているのでその説
明を省略するが1. DAI Uデイジタルスイツ°チ
SRIに設定された数値に比例する′電流を出力する電
流出力型1)ACである。1) Since the operation of AC is well known, I will omit the explanation, but 1. DAI U Digital Switch is a current output type 1) AC that outputs a current proportional to the value set in SRI.
スイッチ81はオン状態に保たれVcの初期値は0にな
っている。この状態のとき制御処理部CP1が起動され
るとスイッチS1が開放され、スイッチSRIの設定値
に比例する値の1流が石、流出力型1)AC(1)At
)から出力されてコンデンサCl上充電するのでVc
は第4図に示すように変化する。The switch 81 is kept on and the initial value of Vc is zero. In this state, when the control processing unit CP1 is activated, the switch S1 is opened, and the first flow of the value proportional to the setting value of the switch SRI is a stone, the outflow output type 1) AC(1) At
) and charges the capacitor Cl, so Vc
changes as shown in FIG.
ランプ甫、圧Vcの傾斜は゛〜流出力型DAC(DAI
)からのT#L流によって定められるが、この電流は、
たとえばディジタルスイッチSR1が2進nビツトの数
値全設定できるとすれは、Vx”のステップで、0乃・
至1−1/!”の間に2n 種類の電流値をとることが
できるのでランプ電圧の傾斜を正確にかつ微細に調整す
ることができるっ電圧Vcを利得の安定化された粘゛幅
器A1で増幅して出力する。The slope of the ramp voltage and pressure Vc is ~ outflow type DAC (DAI
), this current is determined by the T#L current from
For example, if the digital switch SR1 can set all binary n-bit values, in steps of "Vx", 0 to
To 1-1/! Since it is possible to take 2n types of current values between 1 and 2, it is possible to accurately and finely adjust the slope of the lamp voltage.The voltage Vc is amplified by the gain stabilized amplifier A1 and output. do.
なお、第3図にはSKI 、 CPl等をハードウェア
として示し、SRIの設定ハ手動によるとして説明した
が、計算機のプログラムで、これらの部分を構成できる
ことは申す1でもない。Although the SKI, CPl, etc. are shown as hardware in FIG. 3, and the setting of the SRI is described as being done manually, it is of course possible to configure these parts using a computer program.
第5図はこの発明の他の実施例を示すブロック図で、第
3図と同一符号は同−又は相当部分を示し、1)C1は
計算機からデータの送出および制御を行うだめのデータ
バスとコントロールパス、DA2μ市1圧出力型LIA
C、DB2はDA2に入力データを送るデータバス、S
3はSlと連動するスイッチである。FIG. 5 is a block diagram showing another embodiment of the present invention, in which the same reference numerals as in FIG. Control path, DA2μ city 1 pressure output type LIA
C, DB2 is a data bus that sends input data to DA2, S
3 is a switch that operates in conjunction with Sl.
データバスDB2によって伝送されたディジタル信号の
表す数値に比例する電圧が電圧出力型DAC(DA2)
から出力されその電圧値までコンデンサC1を充電して
いる。このときCPlの動作によ!1lS1は開放され
、S3はB側接点に接続されデータノ(スDBIによっ
て伝送されたディジタル信号の表す数値に比例する電流
が電流出力型DAC(DAI)からコンデンサC1を充
電する。A voltage output type DAC (DA2) outputs a voltage proportional to the numerical value represented by the digital signal transmitted by the data bus DB2.
The capacitor C1 is charged to that voltage value. At this time, depending on the operation of CPl! 11S1 is open, S3 is connected to the B side contact, and a current proportional to the value represented by the digital signal transmitted by the data node (DBI) charges the capacitor C1 from the current output type DAC (DAI).
第6図は第5図に示すコンデンサC1の電圧変化の一例
を示す図で、t=0以前はVC= VAに保たれ、t=
0から1=10 まで所定電流値で充電され、t =
tlからt = t2’Eでは充電電流を零とし、t
= t2 においてスイッチS1をオン状態にしてVB
t−7JOえ、t=t3”t’81に、t7.83 k
接点B側に接続し1=0〜1=1□ 期間よりも大きな
゛電流で充電する場合を示している。FIG. 6 is a diagram showing an example of the voltage change of capacitor C1 shown in FIG. 5. Before t=0, VC=VA is maintained, and t=
It is charged with a predetermined current value from 0 to 1=10, and t=
From tl to t = t2'E, the charging current is zero, and t
= At t2, switch S1 is turned on and VB
t-7JO, t=t3"t'81, t7.83 k
This shows the case where the battery is connected to the contact B side and charged with a larger current than the period 1=0 to 1=1□.
以上のようにこの発明によれば電流出力型のDACの出
力電流でコンデンサを充電したので、ランプ電圧の傾斜
を正確かつ微細に設定することができる。As described above, according to the present invention, since the capacitor is charged with the output current of the current output type DAC, the slope of the lamp voltage can be set accurately and finely.
第1図は従来の装置を示す回路図、第2図は第1図の回
路の出力電圧と時間との関係を示す図、第3図はこの発
明の一実施例を示すブロック図、第4図は第3図の回路
の出力電圧と時間との関係分示す図、第5図はこの発明
の他の実施例を示すブロック図、第6図は第5図の回路
の出力電圧と時間との関係を示す図である。
C1・・・コンデンサ、1)Al・・・電流出力型1)
AC。
1)A2・・・電圧出力型DACっ
尚、各図中同一符号は同−又は相当部分を示す。
代理人 大岩増雄
第1図
袂
を二〇 □時間tFIG. 1 is a circuit diagram showing a conventional device, FIG. 2 is a diagram showing the relationship between the output voltage and time of the circuit in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. The figure shows the relationship between the output voltage and time of the circuit in Figure 3, Figure 5 is a block diagram showing another embodiment of the invention, and Figure 6 shows the relationship between the output voltage and time of the circuit in Figure 5. FIG. C1...Capacitor, 1) Al...Current output type 1)
A.C. 1) A2...Voltage output type DAC In each figure, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa 1st illustration 20 □ Time t
Claims (1)
の数値を衣すディジタル符号を入力し当該数値に比例す
る値の′小流を出力する電流型ディジタルアナログ変換
器と、このディジタルアナログ変換器の出力…流により
上記コンデンサを充1M1する手段とを備えたランプ電
圧発生装置。 (21コンデンサに初期嘗、圧を設定する手段は、尚該
コンデンサ全放電することによって零の初期′電圧を設
定することを特徴とする特許請求の範囲第1項記載のラ
ンプ電圧発生装置、 (3)コンデンサに初期宙、圧を設定する手段は、任意
の数値を表すディジタル符号を入力し当該数値に比例す
る値の山王を出力する電圧型ディジタルアナログ変換器
と、このディジタルアナログ変換器の出力電圧を上記コ
ンデンサの初期市、圧とじて設定する手段とを備えたこ
とt特徴とする特許請求の範囲オニ項iピ載のランプ電
圧発生装置。[Scope of Claims] (1) A current-type digital-to-analog converter that includes means for setting an initial voltage in a capacitor and a digital code representing an arbitrary value and outputs a small current proportional to the value. and means for charging the capacitor 1M1 with the output current of the digital-to-analog converter. (21) The lamp voltage generator according to claim 1, wherein the means for setting the initial voltage in the capacitor sets an initial voltage of zero by completely discharging the capacitor. 3) The means for setting the initial pressure in the capacitor is a voltage-type digital-analog converter that inputs a digital code representing an arbitrary value and outputs a value proportional to the value, and the output of this digital-analog converter. 2. The lamp voltage generator according to claim 1, further comprising means for setting the voltage based on the initial voltage of the capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7241183A JPS59198022A (en) | 1983-04-25 | 1983-04-25 | Ramp voltage generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7241183A JPS59198022A (en) | 1983-04-25 | 1983-04-25 | Ramp voltage generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59198022A true JPS59198022A (en) | 1984-11-09 |
Family
ID=13488509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7241183A Pending JPS59198022A (en) | 1983-04-25 | 1983-04-25 | Ramp voltage generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59198022A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5325107A (en) * | 1988-11-30 | 1994-06-28 | Sharp Kabushiki Kaisha | Method and apparatus for driving a display device |
JP2006087059A (en) * | 2004-09-14 | 2006-03-30 | Nippon Precision Circuits Inc | Apparatus and method for generating equaly spaced pulse train |
CN100424996C (en) * | 2003-09-29 | 2008-10-08 | 三洋电机株式会社 | Ramp voltage generating apparatus and active matrix drive-type display apparatus |
-
1983
- 1983-04-25 JP JP7241183A patent/JPS59198022A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5325107A (en) * | 1988-11-30 | 1994-06-28 | Sharp Kabushiki Kaisha | Method and apparatus for driving a display device |
CN100424996C (en) * | 2003-09-29 | 2008-10-08 | 三洋电机株式会社 | Ramp voltage generating apparatus and active matrix drive-type display apparatus |
JP2006087059A (en) * | 2004-09-14 | 2006-03-30 | Nippon Precision Circuits Inc | Apparatus and method for generating equaly spaced pulse train |
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