JPS59197943A - System for detecting address space of memory - Google Patents

Abstract

PURPOSE:To identify a packed address space and surely detect an effective address space in accordance with the change in a memory address space, by writing a prescribed data pattern in a memory space and reading out said pattern. CONSTITUTION:A central controller 12, ROM 14, RAM 16 as a main storage device and I/O interface 18, further a connector 30 are connected with the system bus 10 of the address space detecting system of a memory. An RAM 26 used as a storage device for extension is connected to the connector 30 attachably and detachably. This system is constituted in such a way that each of the RAMs 16 and 26 can be used as the work area of the CPU 12. Moreover, this system is constituted so that an address is appointed by the address bus 20 of this system and a prescribed data pattern is written in the RAM 16 or RAM 26 through a data bus 22, and then, the data is read out. In addition to the above, an effective address space is accurately detected in accordance with the change in a memory address space and the expansion and contraction of the system are made easier.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting a memory address space, and particularly to a method for detecting a memory address space in a processing system in which the address space can be changed, that is, expanded or contracted by changing the hardware configuration of the memory. The present invention relates to an address space detection method.

Stirrup Some devices can be detachably connected via connectors. Such memory expansion or contraction is generally applied to random access memory (RA), and the address space that can be used as a processing unit's work area can be easily expanded or contracted by attaching or detaching an option hold. .

Processing units generally use read-only storage (RO) to keep track of memory status and use memory areas effectively.
M)'s puto loader is equipped with a memory check function. However, conventional memory checking methods can only check fixed address spaces.

For example, if the configuration is configured to check only the address space of the main board, when the address space is expanded by installing an option board as described above,
The added address space will be ignored and no memory check will be performed for that part. Also,
In a method in which a check function is prepared in advance for the address space of insertable option boards, if no option board is inserted, a memory failure will be identified during the memory check operation, and the memory check operation cannot be performed normally. . Therefore, it is necessary to constantly grasp the entire valid address space in response to changes in the memory address space, that is, expansion or contraction, and to be able to check the memory.

Stop--1 The present invention aims to eliminate the drawbacks of the prior art and provide a memory address space detection power formula that can accurately detect a valid address space in response to changes in the memory address space. purpose.

DETAILED DESCRIPTION OF THE INVENTION The structure of the present invention will be described below based on one embodiment.

Referring to FIG. 1, a processing system to which the memory address space detection method of the present invention is applied is shown as an example.
Central processing unit (CPU) 12, R on system bus 10
An OM 14, a RAM 16 as a main storage device, and an input/output device (Ilo) interface 18 are connected. System path 10 is at[/sufhes 20,
It consists of a data bus 22 and an instruction bus 24.

RAM 16 is the main storage device installed in the tree system (for example, as a main board from the beginning).
On the other hand, another additional storage device mounted on an option board, for example, is indicated by a dotted line as RAM 28. RAM 28 is removably connected to system bus 10 by connector 30. Expansion RAM is 1
The unit is not limited to one board, but can be increased by the number of connectors provided on the bus 10. In the non-explanatory embodiment shown here, it is assumed that the RA has a storage capacity of 16 to 192 bytes, and that the RAM 2B can be expanded in units of 84 bytes. These memory spaces, such as RAMs 18 and 26, are used as work areas for CPU 12.

The ROM +4 stores control and processing programs for controlling this system and performing specific processing, and also stores therein a memory check program for detecting memory address space according to the present invention.

For example, as shown in Figure 2, the absolute address 00000
192KB from H (hexadecimal notation) to 2FFFFH
(byte) is implemented, and the storage area for absolute addresses after that is not implemented. In the figure, the mounted parts are shown by solid lines, and the unmounted parts are shown by dotted lines.

In the US embodiment, the memory check program of the ROM 14 writes data of a predetermined pattern to a predetermined storage location, for example, the start address, of each storage area of 114 KB units, ie, memory segment, on the address bus of the memory, in that segment. Next, a read operation is performed by specifying the same start address, and in response, it is checked whether the data returned from the system bus is in this predetermined pattern, and a valid address space is detected. In general, since multiple memory chips can be mounted on one memory board 1, it is better to set the size of this segment equal to the size of the memory chip rather than setting it equal to the size of the memory board. is advantageous.

This will be explained in more detail with reference to the flow diagram of FIG. 3 and the functional block diagram of FIG. 4. In both figures, corresponding steps and blocks are designated with the same reference numerals. When the memory check program is started, first, each segment is initialized (step 50), and then the start address 0OO of the first segment 40 (FIG. 2) is set by the address bus 20.
For example, specify OOH (i.e., all binary "
0'') is written (52). Note that the above-mentioned predetermined pattern does not need to be particularly limited to this example, and may be any other pattern. Next, the CPU 12 selects the same segment 4.
The first address 0OOOOH of 0 is specified and the contents thereof are read onto the data bus 22 (54), and it is checked whether the read data is OOH or not (56).

In this system, when a write operation is performed to an address where no real memory space exists, a predetermined pattern of data is sent to the data bus 22, such as FFH (binary full [IJ]).
is configured to be returned. This is an additional RA
In the state where 26 is not connected, this may be done, for example, by leaving the connector terminal of the helical connector 3o open or holding it at a predetermined reference potential. This pattern does not need to be particularly limited to this example, and may be any other pattern. Therefore, in the above example, the absolute address 0O
In a read operation that specifies OOOH, since the address space actually exists, OOH should be returned to the data/circle space 22.

If 00H is returned, control moves to the next segment 4.
The same detection operation is performed for 2. In this example, 4
An absolute address in the memory space is specified by the contents of a digit segment register (not shown) and the contents of a 4-bit offset register (not shown). Therefore, the starting address IQOOOH of the next segment 42 is designated by adding 100OH to the contents of the segment register (60).

In this way, OOH is added to the start address of each segment.
is written and read out, and if OOH is read out, this is repeated until the contents of the segment register reach FOOOH (58). If the contents of the segment register reach FOOOH, this memory check operation has been performed for all segments that can be specified with 16 bits in the unimplemented example, that is, the entire address space, and the check sequence is finished and other processing is started. Transition.

By the way, if 00)1 is not detected in step 56, the CPU 12 checks whether the data received from the data bus 22 is FFH, that is, all binary "1"s (62). In this embodiment, as described above, the bus connector 30 (FIG. 1) is configured so that when a write operation is performed to a location where no address space exists, FFH is returned to the data bus 22 as a predetermined pattern. Therefore, if data other than 00H or FFH is returned to the database 22, there is a possibility of a memory failure. ” is displayed, error handling is performed, and the operator waits for instructions (68).
.

However, if the FFH is returned, the non-existent
Since there is a possibility that the interpolation operation was performed on the address space, that is, the invalid address space, the control moves to the next step, AB 64, to further confirm this.

For example, in segment 44 of FIG. 2, an address space exists, so OOH is detected in step 56. However, since segment 46 does not exist, if an OOH write operation is performed to its first address 30000H, FFH
should be returned. Once the FFH is returned, step 64 includes all memory locations of that segment 48,
That is, an operation is performed to write OOH to the 84 KB storage location from absolute address 30000H to 3FFFFH. Next, the CPU 12 addresses all storage locations of the same segment 46 and performs a read operation of their contents (function block 70, No. 41N).

In this example, since there is no real address space in segment 4B, FFH should be returned to data bus 22. Therefore, in step 66, it is determined whether or not FF)I has been returned, and if FFI() has been returned for all addresses of the segment 46, it is determined that the memory space does not exist.Therefore, the CPU 12 46 and up to segment 44 are identified as valid memory space (function block 72, FIG. 4).
. This ends the memory check sequence and moves on to the next process. Furthermore, if data other than FFH is returned from any storage location, it is determined that some kind of memory failure has occurred, and the above-mentioned error display or processing is performed (68).

As described above, according to the present invention, the installed address space is identified by inserting a predetermined data pattern into the memory space and reading it out. therefore,
A valid address space can always be accurately detected without being affected by changes such as expansion or contraction of the memory address space. In addition to this detection operation, an operation test of the memory function can also be performed. Therefore, the memory address space detection method according to the present invention can be effectively applied to small computers, especially operating systems such as Japanese AB and foreign language word processors, office computers, personal computers, and Teletex Narahi electronic typewriters. can.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a processing system to which the memory address space detection formula according to the present invention is applied; Fig. 2 is a memory configuration diagram for explaining the address space; Fig. 3 is a memo according to the present invention. FIG. 4 is a flow diagram showing a control flow for executing the address space detection method of No. 1, and FIG. 4 is a functional block diagram showing functional blocks for executing the control shown in FIG. 3. Explanation of the symbol for "branch 1" 123. Central processing unit 14.9, read-only storage 18.2B, random access memory 20, . . . address bus 22, . . . data bus 309. Connector 40...Memory Segment Patent Applicant Ricoh Co., Ltd. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claim] A method for detecting a memory address space in a processing system in which the address space of a memory including a plurality of storage areas can be changed depending on the storage area. A predetermined storage location in the storage area is addressed to write a predetermined pattern of data, then the storage location is addressed to perform a read operation, and the data is returned in response to the continuous read operation. A memory address space detection method, characterized in that a valid address space in the memory is detected by detecting whether or not a take has the predetermined pattern.