JPS5919648B2 - Frequency multi-step control circuit of digital frequency controlled oscillator - Google Patents

Description

Detailed Description of the Invention This invention is a system in which the oscillation frequency of a PLL controlled oscillator is electrically controlled using adjustment pulses. This relates to the configuration of a circuit that operates so that the value changes in large steps.

This type of frequency adjustment means can be used, for example, by intermittent contacts linked to the rotation of a knob, or by intermittent light beams from a photocoupler by rotating a disc with slits, and the generated electrical pulses are converted into U/D (up/down) counters. By presetting the output of each digit in addition to the corresponding digit of the programmable counter of the PLL oscillator to be controlled, the oscillation frequency for each adjustment pulse is equal to the minimum frequency change of this system. It changes in steps.

To put this concretely, the frequency i step of the PLL oscillator used as a local oscillator for SSB communication equipment is 10
0H2 is a little too rough and unsatisfactory, and 1OH2 is satisfactory with the smoothness of the frequency change, but if you want to change the frequency significantly, you have to turn the knob a lot.
This has the inconvenience of taking time.

In order to compensate for this, there is a means of increasing the amount of frequency change by one pulse by providing a fast forward switch, but this has the unavoidable drawback of complicating the operation.

In this invention, for example, when one rotation of the knob changes slowly for more than 1 second, fine adjustments can be made by changing the frequency by 10H2 per pulse. By automatically increasing the amount of change such as 1kHz, combined with the speed of rotation, it is possible to make a large frequency change in a short time.
When the rotation speed is reduced near the target frequency, the amount of change is 1
Since the pulse frequency is 10 Hz, it is convenient to use because fine tuning is easy, and the operation feels natural.

An example of the configuration of this system is shown in FIG.

In the figure, the output 31 of the clock signal oscillator 1 is a clock signal with a period T, and the shaping stage 2 generates a pulse 32 with a period T every time the waveform rises or falls.
This is the reset signal.

The counter 3 measures the pulse 21 from the regulator 20 and outputs the pulse 22 at each predetermined progression. However, when the amount of change in the regulator is small and the number of pulses 210 generated is small, the counter 3 measures the pulse 21 from the regulator 20 and outputs the pulse 22 within the reset signal 320 cycle. Output 22 is not generated because the predetermined advancement of 3 is not reached.

In other words, the generation of the output 220 indicates that the amount of change in the regulator 20 is greater than or equal to the predetermined value.

This predetermined value is the number of pulses of the input 21 within the period of the reset signal 32, so it can be set arbitrarily, but if the base number is small, a sudden change will occur due to the increase or decrease of one pulse, so the base number of the counter is The value should be larger than a certain level, and a decimal counter that is generally used in practice is appropriate.

Retriggerable MSMV (monostable multi-bye break)
4 is the AND of the adjustment pulse 21 circuit with its output when stable.
The gate 5 is normally held on the step side, and the PLL oscillation circuit 1
A pulse 25 is applied to the least significant digit of the U/D counter 12 which controls the programmable counter 11 of 0, resulting in a frequency change of 1OH2 per 1 pulse, for example.

Additionally, the sum and difference operation states are selected by a signal applied to the U/D terminal.

When the output 22 of the counter 3 is generated, it operates as a trigger for the MSMV 4, and its outputs 23 and 24 are inverted by the set retention time t of the MSMV.

Therefore, AND gate 5 switches to the fast forward step side,
An adjustment pulse 26 is applied to the upper digits of the U/D counter.

If you put this in the digit directly above lOH2, 1 pulse is 100H2
It is a feature of this system that the amount of change can be largely selected depending on the digit to which the fast-forward pulse is introduced, such that if it is placed two digits above, it becomes a change of l pulse 1kHz.

MS after the holding time t]Vf■! The stable state will be restored and the gate will return to the normal step, but if a pulse is applied to the trigger during this time, the inversion operation will be maintained by the re-trigger.

Therefore, if the holding time t is set larger than the trigger period T, as long as the pulse 22 is generated, the MSMV will be retriggered and will not malfunction.

FIG. 2 shows an example of the connection of the gate 5 constructed by two ANDs operated by two people.

It goes without saying that the same effect can be achieved by appropriately combining other types of gates.

FIG. 3 is a timing chart of each part of the circuit shown in FIG. 1, and each symbol corresponds to that in FIG.

In range A, the adjustment pulse 21 is connected to the normal step side at the gate 5, and if 3 is a decimal counter, the output pulse 22 is output at the 10th pulse from reset 32■.

In range B, MSMV is inverted for a period of t1, gate 5 is switched, and a fast forward step is operated.

From reset 32■, IO pulse input button output 22■ occurs and MSMV is retriggered for period t2.

Input 21 is 10 between reset 32@ and 32■ in range C
If it is below, 22 will not be output, so at the end of t2, MS
MV returns to a stable state and gate 5 also switches to normal step.

Next, to explain item 2 of the claims, the counter 3 and MSMV 4 in FIG. 4 operate in the same way as described in FIG. 1 and the previous part of the main text,
Furthermore, if the output of the counter 3 is measured by another counter 31 and the output is configured to trigger another MSMV 41, when the number of adjustment pulses 210 generated is small, M
The SMV does not operate and the gate is a normal step, and when the adjustment pulse exceeds a predetermined value, the MSMV is reversed and when switching to the fast forward step, the toro remains the same, but when the adjustment pulse increases further, the counter 31 increases. Generate output and M
SMV41 is inverted.

Therefore, by combining the operations of MSMV4 and 41, the gate 53
By applying the normal step output to the lowest digit of the U/l counter 12, inputting the fast-forward output of the gate 54 to the immediately higher-order digit, and inputting the ultra-fast-forward output of the gate 55 to the two upper digits, the amount of generation of adjustment pulses can be adjusted. Accordingly, the amount of change in frequency step can be automatically changed in three stages.

The gate 56 is an auxiliary gate that combines the operations of MSMV4 and 41 to sequentially operate 53, 54, and 55. Furthermore, by adding a counter, MSMV, and gate, it is possible to switch over 4 stages. Similarly, it is possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a configuration example of the present invention, Fig. 2 is a circuit diagram showing an example of a gate circuit, Fig. 3 is a timing chart showing the operational relationship of each part, and Fig. 4 is an example of a three-stage operation circuit. It is a block diagram. 1... Clock oscillator, 2... Shaper, 3, 31.
...Counter, 4, 41-MSMV, 5, 51, 52
゜53.54,55,56...Gate, 10...P
LL oscillator, 11... programmable counter, 12
...U/'D counter.

Claims (1)

[Claims] A multi-digit U/l) counter for controlling a programmable counter that determines the oscillation frequency of an I PLL controlled oscillator includes (a) a source of a pulse signal with a variable period for frequency adjustment; ) a gate circuit for switching the input right of the U/D counter; (c) the gate circuit is switched by the output of a monostable multivibrator that operates with the output pulse of the counter as a trigger; is measured by inputting the pulse signal for frequency adjustment, and is reset by a pulse generated in synchronization with the cycle of the internal clock signal, so that the number of pulse signals for frequency adjustment is equal to the cycle of the clock signal. If the pulse signal is less than a predetermined value, a gate circuit is configured such that the pulse signal is input to the lowest digit of the U/L counter, and the number of pulse signals for frequency adjustment is a predetermined value with respect to the period of the clock signal. In the above case, the pulse signal is
1. A frequency multi-step control circuit for a digital frequency controlled oscillator, characterized in that the gate circuit is configured to automatically switch as if inputting to the upper digits of a counter. 2. Two or more counters according to claim 1(e) are connected in series, and two or more sets of gate circuits are sequentially switched by the output of a monostable multivibrator that operates using the output of each counter as a trigger. A frequency multi-step control circuit for a digital frequency controlled oscillator according to claim 1, characterized in that the circuit has the following circuit configuration.