US3745380A - Apparatus for controlling clock pulses - Google Patents

Abstract

A timing pulse generator, which produces a plurality of timing pulses, is controlled by a series connected arrangement of a monostable-multivibrator and a clock pulse generator. The monostable multivibrator or delay is triggered by an output from the timing pulse generator, so as to render the clock pulse generator disabled for a predetermined period of time, whereby both clock pulses and timing pulses will be inhibited for the predetermined period of time.

Description

United States. Patent 1 91 Kitajima et al.

[ 11 3,745,380 [451 July 10,1973

22 Filed: Sept. 16,1971

21 Appl. No.: 180,994

Related US. Application Data [63] Continuation-impart of Ser. No. 829,589, June 2,

1969, abandoned.

[30] Foreign Application Priority Data June 3, 1968 Japan 43/37850 [52] US. Cl...; 307/260, 307/247, 307/269, 328/48, 328/59, 331/113 [51] Int. Cl. H03k 5/00 [58] Field of Search 307/247, 260, 269; 328/59, 48, 63, 99; 331/51, 113, 145, 173

[56] ReferencesCited UNITED STATES PATENTS 3,383,525 5/1968 Arksey 307/269 3,564,426 2/1971 Anderson et a], 328/48 3,539,926 11/1970 Breikss 328/48 X 3,124,706 3/ 1964 Alexander 1 307/228 3,241,017 3/1966 Madsen et al. 328/48 X 3,323,074 5/1967 Neal 331/113 X 3,443,246 5/1969 Brown et al. 331/113 2,536,035 2/1951 Cleeton 328/59 OTHER PUBLICATIONS Pub 1 A Gated Astable Multivibnator by Kat in Elec tronic Engineering, dated Feb. 1964, pp 103-105 Primary Examiner-Stanley D. Miller, Jr. Attorney-Craig, Antonelli and Hill [5 7 ABSTRACT A timing pulse generator, which produces a plurality of timing pulses, is controlled by a series connected arrangement of a monostable-multivibrator and a clock pulse generator. The monostable multivibrator or delay is triggered by an output from the: timing pulse generator, so as to render the clock pulse generator disabled for a predetermined period of time, whereby both clock pulses and timing pulses will be inhibited for the predetermined period of time.

9 Claims, 6 Drawing; Figures mare- 88 w OSCILLATOR I l l TB'TA PATENTED B 3,745,380

' sum 10F a I I INVENTOR S ATTORNEY5 P1A$ATOSHI Mn'sw KENICHI IOTATIMAAKIRANAGANOI r ig. Mt -QQL CLOCK PULSE OSCILLATOR SE TIMING PULSE Z/GENERATOR MONOSTABLE Cl RC U IT Fig. 3

PATENTED 3,745,380

sum 2 or 3 Fig. 4

P c OCK J MONOSTABLE $5 PlULSE CP C OSCILLATOR F I 3; g2 Ql SE w W Te TA 172 TI t4 tatt| Fig. 5A

,illlllllllllllll PHI-SE8 Lllllllllllllllll T F1 F1 FT n $IT t J1 F1 r1 F1 PLT'Q'E S FL FL n FL t4 T1 [1 F1 F] I Tn men i TIMING i Tm L PULSES Tl w STEP- T W TIMING TB PULSES e INVENTOR5 KENI HI KITA'S'IHAAKIRA NAeANo MAMrost-n marsm Qowk QMtoumQQ; H 122 AITORNEYS PATENTEDJ 1 (975 3, 745.380

sum 3 0f 3 Fig. 5 6

SE I

58 tl t2 CLOCK Illlllll IIIIIIII PULSES I cPZIIIIIIIII IIIIIIII Ir BIT t2 I-I I1 n n TIM -s PULQES t3 I1 I1 F1 I FL 4 FL I'I FL II 'I'II m TIIA DlGlT I T|2 JL TIMING TIZA PULSES I W I T28 E TA M TIMING TB TA PULSES 7TB I INVENTORS KENICHI KITA'J'INA AKIRA NAGANO NAiATO M HITSUI BYQQQQJOMM; H1322 AFFORNEYS APPARATUS FOR CONTROLLING CLOCK PULSES This is a Continuation-in-Part Application of US. Pat. Application Ser. No. 829,589, filed on June 2, l969 now abandoned.

The present invention relates to an apparatus for controlling clock pulses and more specifically to an apparatus for controlling clock pulses for the purpose of stabilizing the operation of a device, the operation of which progresses in accordance with clock pulses, such as dynamic type calculators.

The operation of calculators of, for example, a dynamic type is controlled in accordance with the progress of steps, each covering a certain number of clock pulses. Conventionally, successive clock pulses have been utilized in the operation and a change to another state of operation has been made by means of a gate at the time of switching of steps. In such an apparatus described as above, however, a delay in the operation of the gate arises, resulting in the disadvantage that a given number of the clock pulses can not be utilized in the subsequent step. Such delay also can be the cause of improper operation of the apparatus.

In order to avoid such an erroneous operation, it has been proposed to provide a time interval between one step and the next subsequent step, so that clock pulses can not be fed during the time interval. Though a special register may be provided for the purpose of producing such a time interval, there are disadvantages in that the apparatus is complicated and is expensive.

Furthermore, it has been contemplated to extend the pulse width of the bit timing pulses. However, if the pulse width is extended, there will arise the disadvantage in that the time of operation of the device is lengthened.

An object of the present invention is to avoid the erroneous operation of an apparatus operating in accordance with clock pulses by means of a comparatively simple and economical means. According to the present invention, therefore, an output terminal of a clock pulse generator is blocked for the purpose of stopping the generation of the clock pulses for a' certain time period at the time of a change of operation of the apparatus operating in accordance with the clock pulses and to maintain the duration of the first bit timing pulse of the first digit of the subsequent step for a certain time as will last until the apparatus continues to the next step.

Another object of the present invention is to provide such an apparatus as can adjust the time interval during which the generation of clock pulses is stopped by blocking the output of the clock pulse generator at the time of the change of the operation. Thus, a stabilized and errorless operation is possible even in case of high speed clock pulses and a slow speed gatecircuit.

According to the present invention, in addition to the clock pulse generator and the timing signal generating means for generating step pulses, namely, for generating step timing pulses, digit timing pulses and bit timing pulses, in accordance with the clock pulses means, are provided for producing an output for a certain time period, based upon a step terminating signal supplied from the timing signal generating means and a switching means for blocking or cutting off the clock pulse generating means during the presence of the output of the means for producing the output.

A further detailed description will be made in conjunction with a preferred embodiment of the present invention with reference to the accompanying drawings, in which;

FIG. 1 illustrates a block diagram of an embodiment of the present invention,

FIG. 2 illustrates a circuit diagram showing the connection between a monostable multivibrator dircuit and a clock pulse generator, and

FIG. 3 illustrates the wave form of the output obtained from the principal part of the apparatus in accordance with the present invention.

FIG. 4 is a block diagram showing the details of FIG. 1,

FIG. 5A is a time chart showing the operation of a conventional device, the operation of which progresses in accordance with clock pulses, and

FIG. 5B is a time chart showing the operation of the device shown in FIG. 4. I

Referring to FIG. 1, 1 denotes a generator for generating clock pulses CP, 2 denotes a timing signal generator for generating step pulses SP, namely, for generating step timing pulses TA, TB, digit timing pulses T and bit timing pulses t',, t' t and t' as shown in FIG. 4, based upon the clock pulses CP and 3 denotes a monostable multivibrator for generating the output SS for a certain time period and at the same time stopping the generation of clock pulses of the generator 1, based upon a step terminating signal SE generated by the timing generator 2 at the time of a change of steps.

Referring to FIG. 2, the collector of a transistor 10 is connected by means of a lead wire 12 through a resistor 11 to the positive terminal 13 of a DC source, while the emitter of the transistor 10 is connected by means of a lead wire 14 to the negative terminal 15 of the DC source. The collector of another terminal 16 is connected bymeans of the wire 12 through a resistor 17 to the positive terminal 13 of the source, while the emitter of the transistor 16 is connected by means of the wire 14 to the negative terminal 15. The base of the transistor 16 is connected through a variable capacitor 18 to the collector of the transistor 10 and also connected to the positive terminal by way of a variable resistor 11 and by means of the lead wire 12, and the collector of the transistor 16 is connected through a resistor 20 shunted by a capacitor 19 to the base of the transistor l0. p

The monstable multivibrator 3 is constituted of the transistors 10 and I6 and the transistor 16 supplies an output for a certain time period when the step terminating signal SE generated from the timing signal generator 2 of FIG. I at the end of every step is supplied to the transistor 10. The collector of the transistor 16 is connected through a resistor 21 to the base of a switching transistor 22. The emitter of. the transistor 22 is connected by means of the wire 14 to the negative.

terminal I5 and the collector is connected to the base of another transistor 24 constituting the clock pulse generator 1 which will be explained afterwards. The clock pulse genenerator l is constituted of transistors 23 and 24; each collector thereof being connected by means of the lead wire 12 through resistors 25 and 26 respectively to the positive terminal 13 of the source, each emitter thereof being connected by means of the lead wire 14 to the negative terminal 15 and each base being connected by way of resistors 27 and 28 and by means of the wire 12 to the positive terminal 13 of the source. A capacitor 29 is connected between the collector of the transistor 23 and the base of the transistor 24, while a capacitor 30 is connected between the base of the transistor 23 and the collector of the transistor 24. The collector of the switching transistor 22 is connected to the base of one of the transistors constituting the generator 1.

Now referring to both FIG. 1 and FIG. 3, the clock pulses CP are generated by the generator 1 and are fed to the timing signal generator 2. Then the step pulses SP are generated by the timing signal generator 2 in accordance the clock pulses CP as is conventional and the step terminating signal SE is generated at the time of a change of operation as is also conventional. The step terminating signal SE is supplied to the base of the transistor constituting the monostable multivibrator 3, resulting in an output of the transistor 16 for a certain time period, during which the switching transistor 22 becomes conducting. The base of the transistor 24 constituting the generator 1 is grounded by means of the transistor 22 and the transistor 24 remains blocked in a non-conducting state, resulting in cut off of the generator 1, while the transistor 22 is in the conducting state.

Referring to FIG. 3, the step terminating signal SE is fed from the timing signal generator 2 to the monostable multivibrator 3 when each step ends at a time 2,. The monostable multivibrator 3 generates, in accordance with the signal SE, the output SS for a certain time period up to a time during which the generator 1 is cut off. At the time t however, the output SS of the monostable multivibrator 3 becomes zero and the transistor 22 becomes non-conducting, and releases grounding of the base of the transistor 24, i.e., removes therefrom the grounding connection. Accordingly, the generator 1 begins to generate again its signal and the clock pulses CP for the subsequent step are fed to the timing signal generator 2.

The operation hereinabove mentioned will be fully described with reference to FIG. 4 and FIG. 5B. In FIG. 4, the timing pulse generator 2 shown in FIG. 1 comprises the bit timing pulse generating circuit 31, the digit timing pulse generating circuit 32 and the step timing pulse generating circuit 33. In a conventional electronic desktop calculator, as shown in FIG. 58, bit timing pulses (for example, t t t';, and t',), digit timing pulses (for example, T, to T in case of 12 digits) and step timing pulses (TAand TB) are generated by clock pulses Cl and CP, from the circuit 31, the circuit 32 and the circuit 33, respectively, to effect various operations. As shown in FIG. 58, according to the present invention, when one step TA has been changed over to the following step TB, the generation of the clock pulses CP and CP can be stopped for a period between t, to 1,. Accordingly, during this period between I to l a signal (t',B) representative of the first bit of the first digit (T B) during the step TB can be maintained without any change. In other words, the duration of this signal (t,B) can be lengthened.

On the contrary thereto, according to the conventional calculator of a similar type, in the event that the step timing pulse TB is distorted at the starting portion as indicated by the dotted line in FIG. 5A at the time of change-over of the steps, the logical product between the bit timing pulse t' B and the step timing pulse TB which should have been I has a tendency to become 0, resulting in that the calculator is often erroneously operated. However, according to the present invention, as indicated by the dotted line in FIG. 58, even if the starting portion of the step timing pulse TB is distorted at the time of change-over of the steps, the logical product between TB and t B can be ensured to be l since the duration of the first signal (t' B) can be lengthened as hereinbefore described. Thus, no erroneous operation occurs. Subsequently, after the time the generation of the clock pulses can be restarted and, therefore, the bit timing pulses can be transferred from t' B, t' B, t',B in the order so that the normal operation of the device commences.

Thus, the generation of clock pulses is stopped for a time t t when one step has been changed over to the following step whereby the duration of the first bit timing pulse of the first digit of the next subsequent step is maintained for a certain time as will last until the apparatus continues to the next step. The time duration t t, can be adjusted to any value by changing, for example, the pulse width of the pulse obtained from the monostable multivibrator 3. Even in case of high speed clock pulses and a low speed gate circuit, the erroneous operation can be avoided by properly choosing, by way of the variable condenser 18 and the variable resistor 11, the output time of the multivibrator 3 so as to maintain the duration of the first bit time timing pulse of the first digit of a new step.

What is claimed is:

1. An apparatus for controlling clock pulses in a device, the operation of which progresses in accordance with clock pulses and timing pulses, and said apparatus comprises a clock pulse generator means operable to generate clock pulses and a timing signal generator means for generating step timing pulses, digit timing pulses and bit timing pulses in accordance with the clock pulses fed thereto, characterized in that said apparatus comprises further means for providing an output for a certain time period by a step terminating signal obtained from said timing signal generator meansat the time of change in step to maintain the duration of the first timing pulse of the first digit of each new step, and a switching meansfor stopping the generation of the clock pulses in said clock pulse generator means during the presence of the output from said further means.

2. An apparatus according to claim 1, characterized in that the further means comprises a monostable multivibrator including two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.-

3. An apparatus for controlling the generation of clock pulses comprising:

a clock pulse generator for generating respective series of clock pulses; first means, responsive to the output of said clock pulse generator, for generating bit timing pulses, digit timing pulses and step timing pulses, the respective durations of which correspond to preselected intervals of time from clock pulses received thereby; and

second means, responsive to the termination of one of said step timing pulses, for lengthening the duration of the bit timing pulse generated coincident with a subsequent step timing pulse, by preventing the application of the output of said clock pulse generator to said first means for a predetermined period of time.

4. An apparatus according to claim 3, wherein said second means comprises a monostable multivibrator including two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.

5. An apparatus according to claim 4, wherein said second means comprises a transistor switching circuit connected to the output of said monostable multivibrator and the input to said clock pulse generator.

6. An apparatus for controlling the generation of clock pulse comprising:

a clock pulse generator for generating respective series of clock pulses first means, responsive to the output of said clock pulse generator, for generating bit timing pulses, digit timing pulses and step timing pulses, the respective durations of which correspond to preselected intervals of time from clock pulses received thereby;

a monostable multivibrator, responsive to the termiation of one of said step timing pulses, for generating a lengthened pulse of a predetermined duration longer than the spacing between successive clock pulses and second means, responsive to the output of said monostable multivibrator, for disabling said clock pulse generator for the duration of said lengthened pulse.

7. An apparatus according to claim 6, wherein the sum of the durations of said bit timing pulses, in one cycle, corresponds to the duration of one digit timing pulse, and wherein the sum of the duration of said digit timing pulses, for one cycle corresponds to the duration of a step timing pulse.

8. An apparatus according to claim 7, wherein said monostable multivibrator includes two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.

9. An apparatus according to claim 8, wherein said second means comprises a transistor switching circuit connected to the output of said monostable multivibrator and the input to said clock pulse generator.

Claims (9)

1. An apparatus for controlling clock pulses in a device, the operation of which progresses in accordance with clock pulses and timing pulses, and said apparatus comprises a clock pulse generator means operable to generate clock pulses and a timing signal generator means for generating step timing pulses, digit timing pulses and bit timing pulses in accordance with the clock pulses fed thereto, characterized in that said apparatus comprises further means for providing an output for a certain time period by a step terminating signal obtained from said timing signal generator means at the time of change in step to maintain the duration of the first timing pulse of the first digit of each new step, and a switching means for stopping the generation of the clock pulses in said clock pulse generator means during the presence of the output from said further means.

2. An apparatus according to claim 1, characterized in that the further means comprises a monostable multivibrator including two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.

3. An apparatus for controlling the generation of clock pulses comprising: a clock pulse generator for generating respective series of clock pulses; first means, responsive to the output of said clock pulse generator, for generating bit timing pulses, digit timing pulses and step timing pulses, the respective durations of which correspond to preselected intervals of time from clock pulses received thereby; and second means, responsive to the termination of one of said step timing pulses, for lengthening the duration of the bit timing pulse generated coincident with a subsequent step timing pulse, by preventing the application of the output of said clock pulse generator to said first means for a predetermined period of time.

4. An apparatus according to claim 3, wherein said second means comprises a monostable multivibrator including two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.

5. An apparatus according to claim 4, wherein said second means comprises a transistor switching circuit connected to the output of said monostable multivibrator and the input to said clock pulse generator.

6. An apparatus for controlling the generation of clock pulse comprising: a clock pulse generator for generating respective series of clock pulses ; first means, responsive to the output of said clock pulse generator, for generating bit timing pulses, digit timing pulses and step timing pulses, the respective durations of which correspond to preselected intervals of time , from clock pulses received thereby; a monostable multivibrator, responsive to the termination of one of said step timing pulses, for generating a lengthened pulse of a predetermined duration longer than the spacing between successive clock pulses ; and second means, responsive to the output of said monostable multivibrator, for disabling said clock pulse generator for the duration of said lengthened pulse.

7. An apparatus according to claim 6, wherein the sum of the durations of said bit timing pulses, in one cycle, corresponds to the duration of one digit timing pulse, and wherein the sum of the duration of said digit timing pulses, for one cycle , corresponds to the duration of a step timing pulse.

8. An apparatus according to claim 7, wherein said monostable multivibrator includes two transistors each having an emitter, a collector and a base, with the base of one transistor being cross-connected to the collector of the other transistor and the base of the other transistor being cross connected to the collector of the one transistor, while the emitters of each transistor are connected to a source of common reference potential.

9. An apparatus according to claim 8, wherein said second means comprises a transistor switching circuit connected to the output of said monostable multivibrator and the input to said clock pulse generator.

Images