JPS59194661A - Booster circuit - Google Patents

Abstract

PURPOSE:To reduce a voltage loss by employing a depletion type as an FET of the first stage for performing rectifying action. CONSTITUTION:The source of an N-channel depletion type MOSFETQ21 is connected to the drain and gate of an N-channel enhancement type MOSFETQ22 connected in a diode, a capacitor C21 is connected to the node 25 to form a Cockcroft-Walton type field circuit. A pulse voltage is applied from an input terminal 23 through the capacitor C21. The complementary voltage of the pulse voltage is applied to the gate terminal 26 of the FETQ21. The source of the FETQ22 becomes the output terminal 22, is connected to the capacitor C22, and the other terminal of the capacitor C22 is grounded.

Description

[Detailed Description of the Invention] The present invention relates to a booster circuit configured in an integrated circuit, and more specifically, proposes a Cockroft-Walton type booster circuit with low loss. It is something.

For example, in order to use V as a write voltage for non-volatile memory, or to apply it to the gate of a MOS FET switch to lower its on-resistance, a voltage higher than the 4 liters of power supplied to the circuit is required. It may be said that For this reason, it becomes necessary to construct a booster circuit in the integrated circuit. In MIS type integrated circuits, a Cockroft-Walton type booster circuit shown in FIG. 1 has been used. 1st
In the figure, Qor Q+z is an n-channel type enhanced terminal MOSFET with a threshold value of VtE (
〉O), and the gate and drain of each are connected in a diode connection, and the node 15 and F are connected to the source of FETQll and the drain of Q1□.
At the source of E′rQ+□, there is a capacitor c,, l C1
2 is being closely contested. Drain Vi of FETQll
Power supply terminal 11 (power supply voltage VDD), the source of FETQ+□ is output terminal 12, and the other end of capacitor C11 is input terminal +3, capacitor? C, □Other end] 4 is set to ground potential. FET Qu and Q12 are diode-connected, so the drain is connected to the source voltage +■
When the voltage is higher than tE, current flows from the drain to the source, and when the drain voltage is lower than that, these F
ET is turned off.

Fig. 2 (a), (b) and e) v'i input terminal 13 respectively
, changes in the potentials of the node 15 and the output terminal 12 are shown.

When a pulse Lti pressure that changes between 0 volts (!: vDD volts) is applied to the input terminal 13, the 0 volt period t
1, the current flowing from the power supply terminal 11 through the FETQ+□ causes the node 15 to reach the voltage VI) -vtEO. During period t2 when the input terminal is at VDD port, the potential of node 15 is 2 x VDD - VtE
9, FETQu is turned off.

On the other hand, when the voltage at the output terminal 12 is lower than the voltage -vtE at the node 15, FETQ+□ is turned on, and current flows from the node 15 through FETQ and □ to the output terminal 12, thereby charging the capacitor C12, and the node 1
If the current outflow from the output panel 12 is sufficiently small, the potential of the output pantrator 12 reaches 2XVDD 2XVtE.

Therefore, in this circuit configuration, V per stage of diode
There is a drawback that a heavy pressure drop of tE occurs. Moreover, the value of VtE increases as the source voltage of the FET increases due to the low body bias, and the difference between the drain voltage and the source voltage in the diode connection of the FET increases to VtE.
Because the diode's misdirection current rapidly decreases as it approaches IE, the boost output becomes much lower than 2XVDD-2XVtE when driving a current load.

This booster circuit was developed to eliminate these drawbacks, and uses a depletion type FET as the first-stage FET that performs the rectification function, thereby eliminating the drawback of heavy pressure loss as described above. The purpose is to provide

The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 3 shows a circuit diagram of a Cockroft-Forton type booster circuit according to the present invention, in which the source of an n-channel depletion type fviOS FET Q71 is a diode-connected n-channel enhancement type MOS FET. It is connected to the drain and gate of ET QP2, and a capacitor fC2□ is connected to this node 25. The other end of this capacitor C2□ is the input terminal 23, and the 0 port and VDD as shown in Figure 4 ((a))
A pulsed voltage varying between volts is applied. FE
The drain of TQp+ is connected to the power supply terminal 21, and the FET
A complementary voltage [FIG. 4(B)] to the pulse voltage shown in FIG. 4(A) is applied to the gate terminal 26 of Q21. FETQ
The source of 22 is the output terminal 22 and the capacitor c
ps, and the other end 24 of the capacitor C2□ is at ground potential.

As described above, the circuit of the present invention differs from the conventional circuit shown in FIG. The difference is that a voltage is applied to the section.

Next, the operation of this circuit will be explained. When the input terminal 23 and the gate terminal 26 are applied with pulses (pressures) as shown in FIGS.
In this case, the power supply terminal 21 and the gate terminal 26 are at VDD (
DTE FETQtt is turned on. Since FETQ21V is a depletion type transistor, the condition for turning it off is that the gate voltage of FETQy+ is the source voltage +vtD.
This is the case if it becomes lower. Therefore, node 25 is VD
Even if D is reached, the gate' (pressure is -Vt from the set-off condition)
Since it is large by D (Vto > 0), the light weight is large 1d
Flowing /& to C21 becomes IIJ function.

In this way, node 25 reaches VDD as shown in FIG. 4(c).

Therefore, next time the input terminal 28 becomes VDD port.
At 2, the voltage at node 25 rises to 2×vDD.

On the other hand, the voltage at the output terminal 22 is the voltage VtE at the node 25.
If lower, FETQ22 turns on and the current flows to FET0
7g to the output terminal 22, thereby charging the capacitor C2□, and the potential at the output terminal 22 reaches 2 x Vl)o -vtE as shown in Fig. 4). During this time, both the source and drain of FET Q21 become higher than VDD, and since the gate is at 0 port, it becomes an off-state island, and reverse current flow is prevented.

As detailed above, the booster circuit according to the present invention uses a depletion type FET as the first stage FET that performs the rectification function in a Kotukuro-Forton type booster circuit configured using FETs and capacitors in an MIS integrated circuit. , in the rectification 1 operation, the reverse bias V is opposed to l and off 1
As a result, the gate of the FET is controlled so that it is turned on by VtE with respect to the forward bias. It will be done.

In addition, since the first stage's charging current is large, even when the final voltage (2 x Vl)D VtE) approaches, the 1 drop in blood pressure i caused by the load current V can be avoided. In fact, it is possible to obtain an output voltage difference of more than Vtg compared to the conventional circuit.

Although the present invention requires two-phase pulse voltages to be applied to the r'i terminals 23 and 26, it is common for the oscillation circuit to have an inverted O-square signal, and for three or more stages of the external pressure circuit. Since the above type always requires two-phase input, the fact that two-phase pulse voltages are required does not necessarily restore the circuit configuration.

Although the above-mentioned IFiA''c is an FET n-channel type, it goes without saying that a p-channel type can also have a similar configuration.

[Brief explanation of drawings]

FIG. 1 is a conventional circuit diagram, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a circuit diagram of the present invention, and FIG. 4 is a waveform diagram of the production theory (7). Cb+ * Q22・FET C21, C2□−・・
Capacitor Patent Issued by J Kaidai Sanyo Gunki Co., Ltd. Patent Attorney Noboru Kono Inu

Claims (1)

[Claims] 1. In a Kotsukuro-Walton type booster circuit using FETs and capacitors in an MIS type integrated circuit, a depletion type is used as the first stage FE'r that performs rectification, and distorted current operation is performed. For the reverse direction of the IA, the gate of the FET is set to t7 and g, and for the 111 direction of the IA, the gate of the FET is set to -.
A booster circuit characterized in that it has a configuration in which Js is applied.