JPS5919383B2 - analog signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog signal processing device used when linearizing an analog signal from a nonlinear transducer.

The present invention provides a novel analog signal processing device that uses a clock signal whose frequency changes over time and performs arithmetic processing on the analog signal in accordance with the frequency characteristics of the clock signal.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a transducer that converts a measured quantity M such as temperature, flow rate, etc. into an analog signal voltage Ei. It has characteristics.

2 is an integrator, which is composed of a resistor R1, a capacitor C1, an operational amplifier OP, and a resent switch S1.

The signal voltage Ei is applied to the integrator 20 through the switch S2, and the reference voltage Es1 is applied through the switch S3.

A comparator 3 compares the integrator output E2 applied via the switch S4 with zero potential, and drives the switch S in accordance with the comparison result.

4 is a filter circuit consisting of a resistor R2 and a capacitor C2, and the reference voltage Es2 is connected to the input of the switch S5.
is applied to the output terminal OUT via the output signal voltage E
.

It gives rise to 5 is a processor such as a microcomputer, which operates the switch S1 according to a program.
．． S2. S3. A signal cp1°CP2 .S4 is periodically driven as shown in FIG. CP3. It generates CP4.

That is, the processor 5 first generates a pulse signal CP1 that drives the switch S1 by 1, then generates a clock signal CP2 that drives the switch S2 for a certain period of time, and then generates a clock signal CP3 that drives the switch S3 for a certain period of time. At the same time, a signal CP4 for driving switch S4 is generated.

In particular, CP is a lock signal in which both the pulse width and pulse interval are constant and the repetition frequency is constant, while CP3 is a lock signal in which the pulse width is constant but the pulse interval changes with time, and the repetition frequency fr changes with time.
This is a clock signal that changes as s f3...f.

The 0230 frequency characteristic can be freely selected by the data provided to the program memory of the transducer 5. In this embodiment, the rate of increase in frequency is increased over time as shown at the beginning of FIG. It was chosen as a characteristic of the inverse function of .

Note that high-speed, high-precision electronic switches are suitable for the switches 81 to S5.

The operation of the apparatus of the present invention constructed in this way will be explained below with reference to the time chart of FIG.

First, the processor 5, CPl, drives the switch S1 to reset the integrator 2, and then the processor C20 drives the switch S2 for a predetermined time ts1, causing the integrator 2 to integrate the analog signal Ei.

At this time, the constant frequency f of switch S2 and C20.

2, the output E2 of the integrator 2 rises stepwise as shown in FIG. 2A.

Then, the output voltage E2 of the integrator 2 after a certain period of time ts1 has elapsed.
Let τ (-C1R1) be the time constant of the integrator 20, and let Δt be the time during which the switch S2 is on for one clock pulse of the clock signal CP2, as shown in the following equation.

Note that by setting tsl to an integral multiple of the noise period included in the input signal Ei, the influence of noise can be effectively removed.

Subsequently, the processor 5 switches the switch S3. S4 to CF2.
CF2 is driven for a certain period of time ts2, the integrator 2 is made to integrate the reference voltage Es1, the output of the comparator 3 is inverted, and the switch S5 is turned on.

At this time, the switch S3 turns on and off in synchronization with the frequency f1 z f2 x f3...fn that changes with time of CF2, so the output E2 of the integrator 2 changes according to the frequency of CF2 as shown in Figure 2A. It descends stepwise and eventually reaches zero potential.

When the integrator output E2 becomes zero, the output of the comparator 3 is inverted,
Turn off switch S5.

Note that even after the output E2 reaches zero, the integrator 2 continues to integrate the reference voltage Es1 until a certain period of time ts2 has elapsed.

Reference voltage E until integrator output E2 becomes zero
The integral value E8 of 81 is R2 after starting the integration of E8□.
Letting tm be the time it takes for CP3 to become zero, and fr be the frequency of the clock signal CP3, it is given by the following equation.

In equation (2), the integral value E8 is equal to the integrator output E2 in equation (1), so from equations (1) and (2), the time tm is as follows.

This time tm is taken out by the comparator 3 as a pulse width m signal - (where T=ts1+ts2), and drives the switch S.

As a result, at the output terminal OUT of the filter circuit 4, The output voltage E.

occurs. In equation (4), j81gf o p T
y ES1* Since Es2 is a constant value, −
It is possible to obtain an output voltage EOr (2) which has been subjected to arithmetic processing determined by the characteristics of .

- can have various characteristics depending on the data given to the fr program memory of the pro-sensor 5, and as in this embodiment, the characteristics of -r can be made to be an inverse function of the characteristics of the transducer 1. If it is determined that the analog signal electron Ei is linearized, an output voltage Eo proportional to the measured quantity M can be obtained.

The clock signal CP3 generated by the processor 5 in this way
By selecting the frequency fr of the analog signal E
It is possible to easily obtain an output signal Eo obtained by performing desired arithmetic processing on i.

In the above, the case where the frequency of the clock signal CP3 changes with time is illustrated, but as is clear from equation (3), the frequency of the clock signal CP2O may be changed with time and the frequency of CP30 is kept constant;
The frequency of CF2 may also be changed.

For example, around CF2 The wave number characteristic = fr of the inverse function of transducer 1 The frequency characteristics of C20 are set to -f.

By making it proportional to time, it is possible to linearize the analog signal Ei and obtain an output voltage EO proportional to the square root of the measured quantity M.

Note that when the frequencies of C20 and CF2 are constant, the frequencies may be set to zero and the switch S2 or S3 may be left on for a certain period of time.

If the reference voltages Es1 and Es2 are still used in common, the output voltage EO will not be affected by fluctuations in the reference voltage, as is clear from equation (4).

Also, the output voltage E is used as the reference voltage Es1.

If you use , the output voltage E. is proportional to the root r of the value obtained by performing arithmetic processing determined by the characteristic of - on the input type pressure Ei.

Furthermore, if the voltage E・' from the transducer 1' is used as the reference voltage Es1 as shown in FIG. 4, then E, □i
An output voltage Eo associated with / can be obtained.

In this case, the property of -- is ordinal, f.

If it is determined to be an inverse function of the characteristics of transducers 1 and 1', the output voltage Eo will be the ratio M /M of the measured quantities M and M'.
' is proportional to '.

Furthermore, by using a Fort Cobra or the like as the switch s5, input/output insulation can be easily achieved.

Further, in the above description, a case has been exemplified in which a processor is used to generate a clock signal whose frequency changes over time, but the clock signal may be generated using other means.

However, when using a processor, due to recent advances in digital circuit technology, processors such as microcomputers have become smaller and can be obtained at low cost.
This has the advantage that the overall configuration can be made simple and inexpensive.

Furthermore, since the processor has many input/output ports in parallel, it has the advantage of being able to process multiple input signals simultaneously.

As explained above, according to the present invention, since a clock signal whose frequency changes over time is used and an operation determined by the frequency characteristics is applied to the analog signal, an analog signal processing device with a simple overall configuration can be obtained. can get.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are time charts and characteristic diagrams for explaining its operation, and FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 1...Transducer, 2...Integrator, 3...
Comparator, 4... Filter, 5... Pro sensor, 81
~S5...Switch, Ei...Input signal voltage, Eo
-...Output signal voltage, E8...Reference voltage.

Claims (1)

[Claims] 1. An integrator that integrates an analog input signal for a certain period of time via a first switch and then integrates a reference signal of opposite polarity to this human input signal via a second switch, and the output of this integrator becomes zero. means for detecting the integration time of the reference signal until the input signal is reached by a comparator and converting it into a pulse width signal corresponding to the input signal; and means for converting the pulse width signal from the comparator into an analog signal and outputting it; means for driving one or both of the first switch and the second switch with a clock signal whose frequency changes over time, and performing arithmetic processing on the input signal according to the frequency characteristics of the clock signal. An analog signal processing device characterized in that it performs.