JPS59193512A - Dmi modulation/demodulation adaptor - Google Patents

Abstract

PURPOSE:To perform the transfer of data of 2-8 times as much as the conventional quantity without causing any error by recording independently the data signal which applied the DMI modulation to the stereo type tracks of L and R channels and the synchronizing clock. CONSTITUTION:A DMI modulation part 1 contains a DMI modulator 5 and an LPF6: while a DMI demodulation part 2 includes a preamplifier 7, a Schmitt circuit 8, a DMI demodulator 9 and a PLL circuit 10. The demodulation synchronizing clock is delivered from the PLL10, and the demodulator 9 consists of a D-FF16, an EX-OR gate G3 and a D-FF15. For instance, a record part (DMI modulator) 1 uses four TTLICs, four operational amplifiers OPAMP and several units of resistances and capacitors. While a reproduction part (DMI demodulator) 2 uses five TTLICs, four OPAMPs, several units of resistances, capacitors and diodes, and a single PLL crystal oscillator respectively. As a result, the number of component parts is decreased to simplify the circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to provide an adapter for magnetically recording and reproducing digital signals using a general stereo audio cassette tape recorder.

First, the conventional technology will be explained. Conventionally, dedicated data recorders have been used to magnetically record digital data such as data from measuring instruments and external storage devices for small computers.

The disadvantage of data recorders is that they are expensive and are inconvenient to carry and use due to their weight and size.

Furthermore, although commercially available stereo audio cassette recorders are capable of two-channel recording and playback as is well known, they are designed for analog signals and are capable of low-speed data transfer and low-density magnetic recording. However, if data communication signals are directly recorded at high density and then reproduced, many code errors occur.

The main causes of this code error are as follows.

1) Physical characteristics of the tape and head, 2) Mechanical accuracy of the tape and motor running system, and 3) Characteristics of the recorder internals and amblifier.

1. The NRZ method is often used for magnetic recording, but
Commercially available audio output recorders generate many code errors due to performance limitations, making them impractical. NBZ
In this method, if the same take code continues, the magnetization on the tape remains in the same state, which makes 1) synchronized reproduction of bits difficult; 2
) Peak soft occurs at the time of inversion (at the end of a series of identical states), causing problems such as a delay in the rise of the output signal.

The present invention was made to eliminate these problems, and will be described in detail below.

The present invention is an adapter device for recording and reproducing digital signals at high density using a commercially available audio cassette tape and a stereo recorder.
It is characterized by independently recording the data signal and synchronization clock for the R channel track base D M .
The data signal is N
M1 (Differential Mark engineering)
rsion) code, is recorded and demodulated during playback.

Tasoshi DM is defined as the following code format.

The DMI code will be explained with reference to FIG. 6, and the state always inverts at the boundary between each bit of data. When the take is ``1'', there is no inversion in the middle of the bit, and the data is
When IOI+, it is always inverted at the center of the bit.

By converting or modulating the data signal into a D M code, the influence from adjacent bits becomes regular compared to the NRZ system, and peak softness and peak shift are alleviated. Therefore, since magnetization reversals occur constantly, it is easier to synchronize Bebisoto with the NFlz code. Therefore, even if the same code continues, two or more bits of the tape will not have the same magnetization. Next, the circuit configuration and operation of each part of an adapter device embodying the present invention will be explained in detail to facilitate understanding.

FIG. 1 is a block diagram showing an example of the circuit configuration of a DM demodulation adder according to the present invention, which is comprised of a DMI modulation section 1 and a DMI demodulation section 2. The DMI modulator 7 includes a DM modulator 5 (!: LPF (Low passf
ilter) 6, 6 is an input signal, sD is a take signal, and C is a synchronous clock signal. The DMI demodulator 2 has a Buriangua, Nyeminoto cycle'd28, and an IM
I demodulator 9, PLL circuit (Phase 1ock 1
oop circuit) 10 is the gold signal, and 4 is the reproduction signal. Note that 11 is a stereo camera recorder, and the left signal and right signal R112 of the L and II stereo channels are Line in (
Input section), 1 line out (output section).

Figure 2 is a circuit diagram that shows Figure 1 in more detail.
is NOR gate, G2 is EX-OR gate, 1
4 is a D-FF (D type flip-flop), G, ,G,
,, +4 constitute a DM adjusting device.

]-' A demodulated synchronization clock is output from LLTO, and D-FFi6 and EX-〇R gate G3 Zuyo and D-
FF+5 constitutes a DM demodulator. As is clear from these figures, for example, the recording section (DMI modulation section) (1&i TTLIc 4 pieces, operational amplifier (OPAM
P) 4 resistors, several capacitors, and the reproducing section (DM
I demodulator) (2) uses only 5 TTLICs, 4 OPAMP resistors, capacitors, several diodes, and 1 PLL crystal resonator, and the adapter of the present invention has a simple circuit configuration and fewer parts. The feature is that it can be made in large quantities at a low price.

Next, the operation of the DM demodulation adapter will be explained with reference to FIGS. 1 and 2. Further, FIG. 6 is a time chart of the waveforms of each part of FIG. 2, and the symbols 2 and 3 indicated on the left side are the original synchronous chronin C and take signal SD before being input to this adapter. In other words, the digital signals recorded on the cassette tape are the synchronized clock C shown in (2) and the data signal SD shown in (2). These signals ■ and ■ are input to the modulation section 1 of the adapter, and the take signal SD ■ is modulated into the J: beat MI code of the waveform ■ by the action of the gates G, , G, , , and the D-type flunograph. Note that ■ is the delayed clock of ■, and ■
is a DMI modulated code according to the definition above. This code is connected to a low-pass filter 6 and an amplifier (not shown, LPF
May be included in 1. -,), input it to the cassette recorder 11, and then record it in stereo.

Clock ■ and take ■ are recorded independently on each channel of the controller.

When the recorded modulated signals of waveforms (2) and (2) are reproduced, the reproduced output of the recorder 11 becomes clock (2) and data (2). This is because the characteristics of the tape and recorder affect the electrical-magnetic conversion. Therefore, recorder 1
The reproduced output from 1 is input to the DMI demodulator 2, and before being demodulated, it passes through a preamplifier 7 and a Noemino circuit 8, and is shaped into waveforms ① and ②. Next, the synchronous clock is PL
J2 absorbs jitter in L circuit TO (1" LL is 41" known as locked loop) and regenerates clock (2) whose phase is shifted by 9W. As is well known, the PLL circuit 10 synchronizes and locks the oscillation frequency f of a built-in oscillator using the PLL method, and outputs a synchronous clock (2) which is shifted in phase by 90 degrees from (2). By using this playback clock ■ as a demodulation synchronization clock for the DMI code, fluctuations in tape speed and fluctuations in tape running (wow, flutter) can be avoided during playback.
Even if this occurs, the clock will follow, and high-speed jitter due to noise etc. will be absorbed.1 In other words, the demodulated data will not be easily affected by tape running. This point is actually important when reproducing high-density magnetic signals, and as is clear from the experimental results shown below, the method of the present invention is resistant to the effects of signal jitter and is less likely to cause code errors during reproduction. .

Next, the effects of the present invention will be explained using actual measurement examples.

First, current one-way communication is 1200 or 2400 BPS.

This data signal can be directly recorded and played back with a normal audio cassette recorder, but it is not practical at communication speeds of 2400 BPS or higher due to the occurrence of many code errors. Therefore, a dedicated high-performance data recorder must be used to record data in high-speed data communications, but it is expensive and has the inconvenience of being difficult to use due to its size and weight. On the other hand, in the embodiment of the present invention, if the above-mentioned DM modulation and demodulation adapter device and a general small portable stereo power sensor recorder are used, it is highly maneuverable and economical.
Moreover, it is possible to record and reproduce high-speed (2400 to 4800 BPS) data communications.

Explain the effectiveness of Mata microcontrollers and panocontrollers as external memory interfaces.

Currently, hardware computers use monaural cassette recorders, and data is transferred using the FS (Frequency Shift) method at 600 to 2,400 BPS, but the cassette memory of current microcontrollers suffers from fluctuations in tape speed and lack of frequency characteristics. This causes an error to occur during data playback. Although there are drawbacks such as lack of compatibility with other recorders due to the difference in performance of single recorders, these problems can be solved by the present invention. The following table compares the data transfer speeds of cassette tape memories in panocomputers, and it is clear that using the device of the present invention (measured in inches), it is possible to transfer data 2 to 8 times faster than conventional methods. . In order to further confirm this, an MI conversion and demodulation adapter as shown in FIG. 2 was made, and data recording and reproduction at 4800 BPS in the system shown in FIG. 1 was performed using a cassette and a stereo recorder. The experimental results were 480 kHz for 50 minutes on a normal type music tape.
Recording and reproducing data of 0BPS, error bit rate is 3.
A measured value of OX+0' is obtained. Note that if data is recorded and reproduced under the same conditions without using the device of the present invention, the amount of data will be reduced by approximately 1/1.
6 data had code errors (bit errors),
The error bit rate is about 3xiO', which is completely impractical.

As explained in detail above, using the DMI adapter of the present invention, it is possible to transfer 2 to 8 times more data than conventional methods without causing errors, which is a significant practical effect, and also records other synchronous data transmissions. It is expected to have a wide range of applications, including use in devices and measurement data logging devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit configuration example of a DM modulation/demodulation adapter according to the present invention, FIG. 2 is a specific circuit diagram of FIG. 1, and FIG. 5 is a time chart of waveforms of various parts of FIG. 2. 1... DMI modulation section, 2... DMI demodulation section,
6...Input of 1, 4...Output of 2, 5.
...DM modulator, 6...LPF, 7...preamplifier, 8...Schmitt circuit, 9...
DM demodulator, 10... PLL circuit, 11.
...Stereo cassette recorder, 12...11 input section, 16...11 output section, +4.15.16.
・D-type Furinogufurosop. Patent applicant Kokusai Denki Co., Ltd. agent Inuzuka 1 person from outside the university

Claims (1)

[Claims] For a synchronous data signal consisting of a synchronous pulse and digital data, the state is inverted at the boundary of each bit of the data signal, and if the data is 1'', the state is not inverted in the middle of the bit, and if the data is ``0'', the state is inverted in the middle of the bit. A DM modulation section for inverting the MI code, inputting it independently to the L (left) input and B (right) input of a stereo cassette recorder, and digitally recording it on an audio tape, and a stereo cassette. A DM1 modulation/demodulation adapter comprising a DM demodulation section that shapes and demodulates the DM code and clock recorded on the R2 channel of an audio tape of a recorder to obtain the original synchronization pulse and digital data signal.