JPS59191931A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To attain an automatic correction of the DC offset by subtracting the digital value stored in a memory from the A/D converted digital signal. CONSTITUTION:Switches 11 and 12 are closed in a queuing state of A/D conversion by the control signal supplied from a control circuit 20. Then the DC offset is converted into a digital signal by an A/D converter 6 via sampling/holding circuits 3 and 4 and then a changeover switch 5 and then stored to memories 15 and 16 in the form of a DC offset correction amount via changeover switches 13 and 14. In an A/D conversion mode, the A/D converted output is supplied to a digital subtractor circuit 17. At the same time, the data stored in the memories 15 and 16 are also supplied to the circuit 17. Thus the DC offset correction amount undergoes a subtraction. As a result, the data on the DC offset error can be automatically collected in an A/D conversion mode. Thus the DC offset is automatically corrected to obtain an accurate digital signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a device for converting an analog signal into a digital signal, and more specifically, the present invention relates to a device for converting an analog signal into a digital signal. The present invention relates to an analog-to-digital conversion device.

[Background of the invention]

When converting analog signals to digital signals and recording them,
When it is necessary to record a DC component as well, it becomes necessary to consider DC offset. An example of a conventional recording apparatus that takes this DC offset into consideration is shown in FIG. In the same figure, 1°2 is an input terminal to which an analog signal is applied, and the "analog signals input from these input terminals 1 and 2 are supplied to siple bold circuits 5 and 4, respectively. In the circuit 3.4, the clock signal alternately samples and holds the Kugata signal at a predetermined period.Then, the bolded signal level is alternately taken out by the changeover switch 5 at the held timing. Analog-to-digital converter (hereinafter referred to as A/D converter) is supplied to B.A
/ The signal converted into a digital signal by the D converter 6 is recorded on a recording medium (not shown) by a digital recording section 7. To adjust the DC offset, before recording, connect input terminals 1 and 2 to a reference potential point such as a ground point, and
This was done by manually adjusting the DC offset adjustment volumes 8 and 9 by looking at the pattern of the output digital signal from the D converter 6.

This type of manual adjustment requires a lot of time to adjust, and has the problem of not being easy to readjust as conditions such as the ambient temperature of the recording device change, requiring repeated readjustments. . Therefore, it may be possible to automatically perform such adjustment. FIG. 2 shows an example of an analog-to-digital converter that can automatically adjust the DC offset. In the figure, 62 and 65 are amplifiers, which in combination with the capacitor 61 constitute an integrating circuit. 6
4 is a comparator, and 65 is a control circuit.

66 is a gate circuit, 67 is a clock signal generator, and 68 is a counter. Adjustment of the DC offset error caused by the DC offset voltage of the integrator circuit and the comparator 64 is performed by 1.
It is done as follows.

During the standby state before performing analog-to-digital conversion (hereinafter referred to as A/D conversion), the switch 53 is connected to the ground side, the switch 55 is closed, and a feedback loop via the resistor 56 causes an error in the capacitor 60. Maintain voltage. Al1) When the conversion operation starts, the switches 53 and 54
are connected to the input terminals 1 and 2, respectively, and the switch 55 is opened. Therefore, the error voltage is subtracted from the input signal input from the input terminal 1.2 by the amplifier 62. The signal from which the error voltage has been subtracted is sent to the control circuit 65, gate circuit 66, clock signal generator 67, and counter 68.
is converted into a digital signal without DC offset error.

In such an analog-to-digital converter,
In order to obtain an A/D conversion operation without DC offset error even when the A/D conversion operation continues repeatedly for a long time and there is no standby state, it is necessary to increase the capacitance value of the capacitor 60 that holds the error voltage. There is. In order to miniaturize the device or integrate one circuit into an integrated circuit, it is difficult to practically realize that the capacitance 60 must be increased.

[°Objective of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an A/D converter that automatically corrects DC offset in a digital recording device. Δ/ that allows DC offset to be corrected without increasing the conversion repetition period.
An object of the present invention is to provide a D conversion device.

[Summary of the invention]

In order to achieve the above object, the present invention converts the DC offset A/D when an input terminal is connected to a reference potential point such as a ground point, stores it in a memory, and performs A/D conversion according to the input signal. When performing D conversion, the digital value stored in the mesori is subtracted from the AID-converted digital signal and output. Control is performed to collect DC offset error data during a predetermined period. In addition, in order to be able to correct the DC offset correction even during the A/D conversion operation, when updating the correction data as a correction state during the A/D conversion operation, the A/D conversion output is The previous output is retained and output.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a Pronk diagram showing one embodiment of the present invention, and the same functions as those in FIG. 1 are designated by the same reference numerals. Reference numeral 10 is an analog-digital conversion circuit unit having a DC offset correction function, and reference numeral 20 is a control circuit that controls the operation thereof.

In the A/D conversion standby state, the control signal input terminal 18
Switches 11 and 12 are closed by a control signal from control circuit 20 applied to, for example, input terminal 1.2.
The switch 15 is connected to the reference potential point by grounding or the like, and the changeover switch 15 is connected to the contact ■ side. Further, the changeover switches 5 and 14 are simultaneously controlled to switch by the input changeover control signal from the control circuit 20 applied to the control signal input terminal 19. For example, when the input changeover control signal is at B level, the changeover switch 5 is switched to contact I. shall be connected to the side. Further, when the changeover switch 5 is connected to the contact I side, the contact of the changeover switch 14 is connected to the I side. When the selector switch 5 is connected to the contact I side.

The A/D converter 6 includes a sample hold circuit 5° changeover switch 5. And the DC offset including the A/D converter 6 is converted into a digital signal, and the changeover switch 15
and stored in the memory 15 through 14. this is,
This is the DC offset correction amount for input terminal 1. When the input switching control signal reaches the L level, selector switches 5 and 1
4 are connected to the contact ■ side, respectively. At this time, the A/D converter 6 connects the sample and hold circuit 4. Changeover switch 5
, and the A/D converter 6 are converted into a digital signal and stored in the memory 16 as a DC offset correction amount of the input terminal 2. This operating state is A
/ Called D conversion standby state 1 For example, control circuit 2o
It is assumed that this state occurs when a -'' level is applied to the control signal input terminal 18 from .

To perform A/D conversion of the input signal, set the control signal applied to the control signal input terminal 18 to 'L' level, open the switches 11 and 12, and connect the selector switch 15 to the contact point (■). .

Accordingly, the A/D conversion converter specific power is applied to the digital subtraction circuit 17.

When the input switching control signal applied to the control signal input terminal 19 is at R level, the input signal supplied to the input terminal 1 is A/D converted and supplied to the digital subtraction circuit 17,
At the same time, the data stored in the memory 15 is also supplied to the digital subtraction circuit 17 to subtract the DC offset correction amount. Also, when the input switching control signal becomes 'L' level,
The input signal supplied to input terminal 2 is A/D converted,
The data stored in memory 16 is subtracted to correct the DC offset.

The control circuit 20 controls the standby state before the Δ/D conversion and the operation of the A/D conversion.
This operation will be explained using the timing chart of FIG. a is a signal instructing recording output from the operation key 21 that controls the operation of the entire device;
is applied to When this signal α is at B level, a recording state is entered. b is an input switching control signal applied to the control signal input terminal 19, which corresponds to the sampling cycle of the input signal to be Δ/D converted.

C is the standby state applied to the control signal input terminal 18 and A/
D conversion operation state. It's a signal.

A state in which no recording operation is commanded, that is.

When the output signal α of the operation key 21 is at the "L" level.

If the control signal C applied to the control signal input terminal 18 is set to a - level as shown in the figure, the analog-to-digital conversion circuit section 10 is in a standby state and used for DC offset correction, as described above. This is the correction data collection operation.

When a recording command is issued and the signal α goes to H level, the control signal C is inverted to L level and the input signal is switched to the operating state for A/D conversion, but the timing of this switching is as follows:
If it is performed during A/D conversion operation, errors will occur in the digital signal.

The timing when the Δ/D conversion operation is not performed, for example, as shown in the figure, is made to coincide with the timing at which the input switching control signal is inverted.

In this way, data for DC offset correction can be collected when entering the recording state.

In the recording state, correction is automatically performed based on this correction data.

Note that when the standby state is controlled by the control circuit 20,
In addition to the operation indicated by the control signal C, R is controlled for a predetermined period after entering the recording operation as indicated by the signal dK.
The standby state may be set as a level, or the standby state may be set during a period when no recording operation is commanded and during a certain period after the recording operation is commanded, as shown by the signal e.

According to this embodiment, data for correction is collected before the recording pressure every time the recording state is manipulated, and direct current offset can be automatically corrected, so it is possible to record accurately A/D converted signals. becomes.

Next, A /
A further improved embodiment of the D conversion device will be described.

FIG. 5 is a block diagram showing another embodiment of the present invention. In the previous embodiment, correction data is collected prior to recording, whereas in this embodiment, the A/D for recording etc. It is possible to update the correction data even during the conversion operation, and even if the DC offset value fluctuates during the operation due to continuous Δ/D conversion operation and the ambient conditions change, accurate A/D conversion is possible. This enables D conversion.

This will be explained below using the drawings.

49 is an analog/digital conversion circuit section.

It has almost the same configuration as the analog-to-digital conversion circuit section 10 shown in FIG. 25 is a holding circuit whose operation is controlled by the control circuit 24 together with the analog-to-digital conversion circuit section 49. The feature of this embodiment is that before the A/D conversion operation, data collection operation for DC offset correction is performed as in the previous embodiment. The correction data collection operation (hereinafter simply referred to as correction operation) is performed even in a certain period.

During this correction operation, the holding circuit 23 holds the previous value so as not to output the DC offset correction data.

In the analog-to-digital conversion circuit section 49, the changeover switches 26, 27, and 29 are switched when performing a correction operation, and are operated by a control signal from the control circuit 24. At this time, the changeover switches 26 and 27 connect the inputs of the sample and hold circuits 55 and 36 to a reference potential point, such as by grounding them, and convert the DC offset amount at each input of the two input terminals 1 and 2 to the A/D converter. 57
convert it into a digital signal. Then, the DC offset correction data is alternately stored as a digital signal in the memories 59 and AO through the changeover switch 50 which operates in synchronization with the changeover switch 28 for input changeover. When the changeover switches 26, 27, and 29 are switched to the state shown in the figure to enter the A/D conversion operation state, the input signals from the respective input terminals 1 and 2 are alternately q/D converted, and as shown in the memo I) sq+to The correction value stored in is subtracted by a digital subtraction circuit 68 and outputted through the terminal 22 as an accurate digital signal. The above operation is the same as that of the analog-to-digital conversion circuit section 10 in the embodiment described above. The signal converted into an accurate digital signal is normally outputted to an output terminal 25VC through a holding circuit 25, and then recorded or transmitted via a recording circuit or a transmission line (not shown) in a control circuit 24 where an A/
Not only is a control signal applied to the control signal input terminals 31 to 56 to perform a correction operation only when starting D conversion, but also % A/
Even while the D conversion operation continues, a control signal for performing the correction operation is generated at a time interval longer than the repetition period of the A/D conversion. At this time, a control signal is also supplied to the holding circuit 23 to perform the operation of holding the previous value, so that the immediately preceding VC
The A/D converted digital signal output is held and outputted to the output terminal 25.

When input signals are to be A/D converted alternately using two input terminals 1.degree.2 as shown, it is convenient to configure the holding circuit 25 as shown in FIG. 6. In the figure, 41 to 43 are changeover switches controlled by the same control signal as the input changeover control signal that is supplied from the control circuit 24 to the control signal input terminal 54 of the analog-to-digital conversion circuit section 49 and controls the changeover switch 28. be. That is, the changeover switches 41 to 43 operate in synchronization with the input changeover that is performed at the repetition period of the A/D conversion operation,
The analog signal supplied from input terminal 1 is sent to A/D converter 57. The digital signal converted by the digital subtraction circuit 38 passes through a switching switch 41, a holding circuit 44, a switching switch 4, and an output terminal. Further, the analog signal supplied from the input terminal 2 is a digital signal converted by the A/D converter 67 and the digital subtraction circuit 38.

The signal passes through the holding circuit 45 via the changeover switch 41, passes through the changeover switch 43, and reaches the output terminal 25. During the correction operation, a previous value holding command signal outputted from the control circuit 24 passes through the changeover switch 42 and sets the holding circuit 44 or 45 in the previous value holding state.

By doing so, the correction operation can be performed not only at the start of the A/D conversion operation when starting the recording operation, but also during the Δ/D conversion operation without changing the A/D conversion cycle. When the recording operation continues continuously for a long time, an accurate digital signal can always be obtained even if the DC offset drifts. FIG. 2 is a block diagram showing an example. The difference from the embodiment shown in FIG. 5 is that a comparator 46 is provided for comparing both the digital signals at the input and output terminals of the holding circuit 260, that is, the terminal 22 and the output terminal 25. The output of the comparator 46 is then supplied to the control circuit 24 to control the point in time when the correction operation is performed during the A/D conversion operation. In the holding circuit 25, A/
The D-converted digital signal is A/D converted.

Since the signal is inputted sequentially in each cycle and outputted with a delay of one A/D conversion cycle, the signal from one cycle before is compared with the signal currently output between the input and output.

Therefore, the two are compared according to the signals supplied to input terminal 1 and input terminal 2, and there is no problem even if the difference between the two is small and the previous value is held and the same signal is output continuously. It is possible to detect the point in time when there is no

That is, the comparator 46 is configured to output a signal when the two compared signals are the same or have a small difference, and the correction operation is permitted only when an output is obtained from the comparator 46. In this way, even if the same digital signal is continuously output during the correction operation, the problem of holding the previous value will not occur when the same digital signal is inversely converted and reproduced into the original analog signal.

As shown in the figure, there are two systems of analog signal input, and two systems of holding circuits 44 and 45 are shown in FIG.
When using, it is also possible to compare each system with the previous value. In addition, the comparator 46 not only detects when the difference between the signals at terminals 22 and 25 is small, but also detects the absolute value to detect when the difference between the two signals is small and the absolute value is also small. It is also possible to In this way, for signals with large absolute values of digital signals, the upper few bits are transmitted,
When using digital companding technology, which transmits the lower several bits of a signal with a small absolute value and inversely converts and reproduces it, if the signal is detected when the absolute value is small and a correction operation is performed, The influence on the reproduced signal caused by performing the correction operation during the A/D conversion operation can be further reduced.

FIG. 8 is a block diagram showing still another embodiment of the present invention, and the difference from the embodiment shown in FIG. 5 is that level comparators 47 and 48 detect the level of the input analog signal.
This is because we have established the following. In this embodiment, the levels of analog signals applied to input terminals 1 and 2 are detected by level comparators 47 and 48, and when the level is a small level below a predetermined value, the control circuit 24 It provides an output to allow corrective action only when the level of the input analog signal is low. Other operations are similar to the embodiment shown in FIG.

With Vcj in this way, when the level of the analog signal before Δ/D conversion is small, the amplitude is emphasized (analog pressure M), A/D conversion is performed, and the digital signal is transmitted or recorded to become a 5-dimensional signal. On the playback side, the digital
This is particularly effective when using an analog companding technique that expands the dynamic range by reducing the amplitude of an analog signal after analog conversion (analog expansion). This is because the correction operation is performed when the signal is small, and the amplification factor of the analog signal is lowered after digital-to-analog conversion, so even if there is a bit change due to the correction operation, the degree of change in the reproduced analog signal is compressed, and the effect This is because O decreases in the level detectors ay, aB in this example.

It is easier to perform detection on the input side of the analog compression circuit, and when analog companding is used, a level comparator is required in the analog compression circuit.
It can also be used as this level comparator.

It is also possible to use the control based on the comparison of the previous value of the digital signal shown in FIG. 7 and the control based on the input signal level comparison shown in FIG. 8 in combination.

According to the embodiments shown in FIGS. 5 to 8, the correction operation is performed not only prior to the A/D conversion operation, but also during the A/D conversion operation.

It becomes possible to perform a correction operation without affecting the conversion operation, and accurate A/D conversion is guaranteed even if there is a fluctuation in the DC offset during operation.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to automatically collect DC offset error data whenever an A/D conversion operation is performed, and it is possible to automatically collect accurate digital offset error data with the DC offset corrected. signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional digital recording device, and FIG. 2 is a block diagram of a conventional analog-to-digital conversion circuit with a function of correcting DC offset errors.
FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is a timing chart for explaining the operation, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram of the present invention. A block diagram showing a specific example of the holding circuit according to the invention, and FIGS. 7 and 8 are block diagrams showing still other embodiments of the invention. 1.2...input terminal, 3, 4.55.36...
- Sample hold circuit, 6.57... A/D converter, 7... Digital recording section i is, i6. s9. a
o...Memory, 17.38...Digital subtraction circuit, 20.24...Control circuit, 25, 411, 45
... Holding circuit, 46... Comparator, 47° Fig. 7 ratio Fig. 3 Fig. 5 Fig. 4Z Fig. 2 Fig. 72

Claims (1)

[Claims] 1. A/D conversion means for converting an analog signal supplied to an input terminal into a digital signal, and a DC offset converted by the A/D conversion means when the input terminal is connected to a reference voltage point. a memory for storing a digital signal corresponding to the digital signal; a subtracting means for subtracting the digital signal stored in the memory from the converted digital signal when converting the analog signal into a digital signal; A of the input analog signal
/ An analog-to-digital conversion device characterized by comprising: means for controlling the input terminal to be connected to a reference potential point to store a digital signal corresponding to a DC offset in the memory when starting D conversion. . 2. The control means always connects the 'input terminal to the reference potential point and stores the DC offset in the memory when no command is given to convert the analog signal into a digital signal and output it. An analog-to-digital converter according to claim 1, characterized in that: 6. After receiving a command to convert the analog signal into a digital signal and output it, the control means connects the input terminal to a reference potential point and stores the DC offset in the memory for a predetermined period. An analog-to-digital conversion device characterized by: 4. An A/D conversion means that converts the analog signal supplied to the input terminal into a digital signal, and when the input terminal is connected to a reference potential point, the digital signal corresponding to the DC offset converted by the A/D conversion means is converted. a memory for storing, and a subtraction means for converting an analog signal into a digital signal and subtracting the digital signal stored in the memory from the converted digital signal and outputting the result;
A holding means for passing the digital signal output from the subtraction means, holding the previous value when a control signal is applied, and outputting the held digital signal; and a DC offset by connecting the input terminal to a reference potential point. An analog-to-digital conversion device comprising: control means for controlling an operation of storing a digital signal corresponding to the above in the memory, and supplying a control signal to the holding means. 5. The control means connects the input terminal to the reference potential point at time intervals longer than the repetition cycle of K A/D conversion during the duration of the operation of converting the analog signal into the digital signal, and calculates the DC offset stored in the memory. 5. The analog-to-digital converter according to claim 4, wherein pressure control is performed to update a digital signal corresponding to . 6. The control means detects a change in the output digital signal, and controls the digital signal corresponding to the DC offset stored in the memory to be updated when the change is smaller than a predetermined value. An analog-to-digital conversion device according to claim 4 or 5, characterized in that: Z The control means detects the level of the analog signal supplied to the input terminal, and when this level is smaller than a predetermined value, updates the digital signal corresponding to the DC offset stored in the memory. Claim 4 or 5, characterized in that
The analog-to-digital converter described in . 8. The control means according to claim 6, wherein the control means has a comparison means for comparing the input and output digital signals of the holding means when detecting a change in the output digital signal. Analog-to-digital converter.