JPS59191339A - Test-facilitating circuit - Google Patents

Abstract

PURPOSE:To enable to perform a test using few input-output terminals by a method wherein input is switched using a latch circuit and a selective circuit. CONSTITUTION:An integrated circuit 21 has input terminals A, B and C, output terminals D, E and F and a test control input terminal T. A latch circuit 212 is connected between the input terminal A and the terminal AA of the inner circuit 213, and a selective circuit 211 is provided between the input terminals A and B and an inner circuit terminal BB. When a test operation is performed, the data to be applied to the terminal AA is inputted to the input terminal A, and said data is latched to the latch circuit 212. Then, the data to be applied to the terminal BB is applied to the input terminal A, and it is then applied to the terminal BB through the intermediary of the selective circuit 211. Then, the data to be applied to the terminal CC is inputted to the input terminal C. A test is performed under this condition. Also, the checking of output is performed through the intermediary of a selective circuit 214.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit configuration of an integrated circuit for facilitating testing when testing an integrated circuit.

[Technical background of the invention and its problems]

It is well known that as the amount of circuitry integrated into one chip increases, the number of input/output terminals on the chip increases.

Currently, integrated circuits with over 100 terminals are common;
Some go beyond the terminal. Conventionally, testers for testing such integrated circuits have been used that have as many measurement terminals as the number of terminals of the integrated circuit. However, increasing the number of measurement terminals on a tester to match the number of terminals on integrated circuits, which will continue to increase in the future, is difficult due to the high cost of testers and the production volume of integrated circuits with a large number of terminals. It is not a good idea, as you cannot hope for a large enough amount to depreciate the amount.

A conventional solution to this problem has been to prepare shift registers corresponding to the number of input/output terminals and incorporate them into the integrated circuit.

An example is shown in FIG. 1, and the principle of its operation will be briefly explained below. First, a few terminals will be used exclusively for testing. In addition, shift registers are prepared in the internal circuit in correspondence with input terminals, and each fritz register 7 constituting the shift register is
The zero outputs (St to S,) are output to the input terminals (A9B, C) during testing, and are connected to the input terminals in a circuit configuration in which they are disconnected at other times.

In the figure, G and ~G3 indicate transfer darts.

During testing, the tester's measurement terminals do not need to be connected to all input terminals of the integrated circuit.

All that is required as inputs are a serial input to the shift register, a clock for operating the shift register, a control input, and a control input for controlling the output of the shift register. When values are set to all the offset registers that make up the shift register by these input terminals,
These values are applied inside the integrated circuit 11 as if they were applied from the original input terminals. For more details on this see e.g. IEEE Te5tC'onferenc.
e (pages 414-424, published NOV 1'982).

However, this method has the disadvantage that the amount of circuitry required for testing is large and the clock system is also complex.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to realize a means for testing the above-mentioned integrated circuit with a small amount of circuitry even with a tester having fewer measurement terminals than the number of input/output terminals of the integrated circuit. shall be.

[Summary of the invention]

In order to achieve the above object, the present invention is configured such that data obtained through a part of an input terminal is inputted internally after being latched by a latch circuit, and after latching, the data is input to another input terminal. It is configured so that it is input into the integrated circuit via a selection circuit in order to substitute for . This configuration makes it possible to test integrated circuits with a small number of input terminals.

[Embodiments of the invention]

The present invention will be described in detail below using FIG. 2 and subsequent figures.

FIG. 2 is a block diagram showing an embodiment of the test facilitation circuit of the present invention.

In the figure, an integrated circuit 21 has inputs A and B.

It has external terminals C, E, and F.

It also has an integrated circuit or test control input terminal T.

Here, A to F and T are not necessarily each one bit (one bit). Below, for the sake of brevity, these are simply A-F.
, T for explanation.

First, we will explain the operation during testing.

The measurement terminals of the tester are connected to A, C, D, F and T. Due to the human control of T, the input selection circuit 211 is set so that A is BB.
It works as shown in the output.

For the input of each test step, first, a data pattern that should originally be applied to AA is set to the A input, and this value is latched into the latch circuit 212. Next K.

The data pattern that should originally be applied to BB is set to AA. At this time, C is set with a data pattern that should originally be set in CC. If the internal circuit 213 is operated in this state, the integrated circuit can be normally tested even if the tester terminal is not connected to B.

In addition, to check the output, select output DD and EE from circuit 2.
By switching at 14 and having the tester read the terminal twice, the integrated circuit can be normally tested even if the tester terminal is not connected to the output E.

The latch circuit 212 has a simpler circuit than a shift register, and the selection circuit can use the transformer 7 add shown as a conventional example in FIG. 1, so the additional circuit for the test shown in FIG. The amount of circuitry is smaller than that of the prior art shown in FIG. 1, and can be constructed more easily.

Furthermore, the input selection circuit 211 is composed of a simple circuit shown in FIG. During testing, input B is always 0PEN
Since it is a state, it can be substituted, which simplifies the circuit.

31 indicates trans7agut.

Here, the input C is directly input to the internal circuit 213 (CC), and the output FF is directly output to the output terminal F. These /4' paths are prepared for application to signals for which there is no timing margin in the internal circuit 213.

Next, a so-called normal operation, which is not a chiad state, will be explained.

During normal operation, the latch circuit 212 passes through input A and directly outputs AA[A, the selection circuit 211 on the input side outputs input B to BB, and the selection circuit 214 on the output side outputs DD to DK output. Set the test control human power T so that the

In the above description of the test, since input B and output E are not connected to the starter, it is not possible to check for poor binding during pankey song, for example. Therefore, in the test after assembly, the changeover switch 41 shown in FIG. 4 is installed outside the integrated circuit board. The operation at this time is to first switch the switch to the A side and latch it into the latch circuit 212 inside the integrated circuit 21. Thereafter, the switch 4) is switched to the B side, but the input side selection circuit 211 inside the integrated circuit 21 sets the test control power T so that B is output to BB. By operating the internal circuit 213 in this state, it is also possible to test for the assembly failure described above.

In the explanation so far, it has been stated that the subject of the present invention is only an integrated circuit. This means that the present invention can also be used for fully custom LSIs such as microcomputers.
This also means that it is effective for semi-custom LSIs such as dirt arrays. In a fully custom LSI, even if the circuit for testing becomes complex, it is possible to avoid increasing the chip area by making mask-to-four-turn design efforts, but with a dirt array, the more complex the circuit, the more the chip area will need to be increased. The number of ports that can be used for internal circuits is reduced. From this, it can be said that the present invention is currently effective for dirt arrays, but it may also be equally effective for fully custom LSIs if the mask pattern design effort becomes difficult to absorb due to the building lock method, etc. Become.

Further, the present invention is effective for testing the A' cutout even when a plurality of chips are mounted on one package.

〔Effect of the invention〕

As described above, according to the present invention, integrated circuits can be tested with a small amount of circuitry and in a simple manner.

Furthermore, since the present integrated circuit can be tested with a tester having fewer measurement terminals than the number of input/output terminals of the integrated circuit, there is no need to use an expensive tester.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the construction of a testability circuit according to the prior art, FIG. 2 is a diagram showing an embodiment of the testability circuit of the present invention, and FIG. FIG. 4 is a diagram illustrating an example of the connection between a tester that inspects all input/output terminals after assembly and an integrated circuit to be measured. 21... integrated circuit, 211, 214... selection circuit,
212...Latch circuit, 213...Internal circuit. Applicant's agent Patent attorney Takehiko Suzue 1 Figure 4

Claims (1)

[Claims] In test mode, for integrated circuits that require input settings,
It has a latch circuit that latches data input to a portion of a plurality of external input terminals, and a selection circuit that selectively outputs a portion of the data that arrives via the input to this latch circuit and other external input terminals. A test facilitation circuit characterized in that data arriving via the latch circuit output, the selection circuit output, and other external input terminals not connected to these two circuits are used as input signals to the internal circuit. .