JPS5918994A - Memory scope - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory scope that displays measurement signals in waveforms.

A memory scope is a device that temporarily stores the instantaneous values of continuously output signals in a memory and displays them.Usually, one type of signal is displayed in waveform. However, since the type of measurement signal often has an isocurve waveform,
Even if two types of signals are displayed simultaneously, there is little risk of confusing them.

The present invention has been made with attention to these points.
Two types of signals are taken out alternately and different types of signals are alternately applied to each signal line of an XY matrix display panel, so that it is possible to display the two types of signals on the same display surface as if they were interlaced.
On the other hand, the display screen is divided into two parts, and two types of signals can be displayed independently on each part.

Embodiments of the present invention will be explained below based on the figures. 1. In Fig. 1, (1) is a changeover switch that inputs two types of signals A and B and switches them alternately; (2) is an amplifier; (3)
is an A/B signal that digitally converts the A and B signals that are input alternately.
D converter, (4) is a memory that stores the digitized A and B signals, +5+ is a trigger circuit that detects the input of signal -υA and 13, and is activated;
5) A counter that outputs a signal for a predetermined period of time, e.g., 1 μsec, for a signal input wave. (7) is a memory write address counter that operates when the output signal of this counter (6) is present, and its output is sent to the multiplexer (8). is added to the memory (4) via the memory (4). A, B(,1j-i
, ]: The operation period of the memory write address counter (7), for example, as mentioned above, the entry into the memory (4) is stopped during 1 μsec. Now the capacity of memory (4) is 64X150bi
t.

Then, a corresponding signal amount is input to the memory (4) within 1 μsec, and the changeover switch (1) operates at a speed corresponding to the signal amount. In the present case, this operation is synchronized with the minimum bit output of the memory write address counter (7). (101 is a coincidence detection circuit and a 6-bit counter (11
1 and the output of memory (4), it outputs a coincidence signal. (121) (122) is - several building output circuit 00)
This is a 150-bit shift register to which the output of Y is added, one register (12,) gives a signal to the even numbered line of the signal line Y, and the other register (122) gives a signal to the odd numbered line. (131) and (132) are 1-line latch circuits, (141) and (142) are X drivers that drive the signal/line Y, and (9) is a memory read address counter.
Its output is applied to a multiplexer (8). (15
1) (152) is a 32-bit shift register that outputs the entire scanning signal -i, which is applied to the scanning line X, and is applied to the scanning line The shift registers (15+) (152) are driven by the output signal from the memory read address counter (9).
5n) (152) to the memory read address counter (9
), the display selector switch indicates whether to connect in series or parallel.
The positions indicated by are parallel.

08) is a matrix display panel that performs display operation by receiving scanning signals and display signals from X drivers (16t) (162) and X drivers (141) (142), and uses a liquid crystal display panel. An example is shown in which the number of scanning lines X is 64 and the number of signal lines Y is 150.

The counting frequencies of the memory read address counter (9) and 6-bit counter 01) are the same, but each time the 6-bit counter (11) counts 64 bits,
One shift operation of the shift registers (12]) (122) is performed. Number of bits of 6-bit count (11): 64
is designed to correspond to the total number of scan lines X. The multiplexer (8) also has a memory write address counter (7).
) and the output of the memory read address counter (9) are added, but of both signals, the former output is given priority,
While this signal is being output, a write operation to the memory (4) is performed.

During the remaining period, it is always in the read state and the memory contents are output in accordance with the output signal of the memory read address counter (9).

Next, the operation when the display changeover switch 07) is in the "single" position will be explained. The two types of signals A and B are serial signals that are alternately outputted via a changeover switch (1), amplified by an amplifier (2), and applied to an A/D converter (3). - The A%B signal output from the power amplifier (2) drives the trigger circuit (5) and operates the counter (6). As a result, the memory corrupted address counter (7) is activated, the multiplexer (8) is switched to the m-feed operation side, and the memory (4) becomes in a writable state. Therefore, during this period, the A and B serial signals digitally converted via the A/D converter (3) are written into the memory (4).

When the writing to the memory (4) is completed, the contents of the memory (4) are read out with the operation of the memory read address counter (9) and the 1-bit counter 0.1+, and the -number output circuit α0) is read out. 1M shift register (121) (122)
will be forwarded to. Shift register (121) (122)K
When the A and B signals for one line are stored, this information signal is transmitted to the launch circuit (1-1) (1-2), the X driver (
14+) (142) to the display spring /I/crystal.

Then, the intersection is selected according to the scanning signal from the X driver (1<5l) (162), and the predetermined intersection is lit. In this way, the waveforms corresponding to the signal A and the signal BK are displayed alternately for each signal line on the display panel o8).

Next, turn the display l, 7I changeover switch (17) to the "double" position u?
The case where it is set to 1 will be explained. In this case, the shift registers (15l) (152) are driven in parallel by the output of the memory read address counter (9), so the display spring /v (1,8) is divided into upper and lower halves, with the upper half being the shift register (152). 15+) and X driver (16t),
The lower half of the dimension is scanned independently by a shift register (152) and an X driver (162). Therefore, the information signal A stored in the even bit positions of the shift register (12t) will appear in the upper half of the display panel (18), and the information signal B stored in the odd bit positions of the shift register (122) will appear in the upper half of the display panel (18). , will be displayed in the lower half of the display panel (18). Figure 2 (a) shows signals A and B on the display screen.
FIG. 3(B) shows a state in which the display screen is divided into upper and lower halves, and the signals A and 13 are divided and displayed in two parts.

The scanning signal X and display signal Y applied to the matrix display panel (18) are expressed as shown in No. 6 (2).

That is, the display signal Yj corresponding to the display point is the scanning signal Xi
, and their phases are opposite.

Note that the effective voltages Vs and Vu applied to the selected point and the non-selected point
Each of s is expressed by the number of scanning lines, and the ratio thereof is as follows, which indicates a constant value. LCD display spring/I/(18)
In this case, the threshold voltage exhibits a unique value depending on the characteristics of the panel itself. Therefore, the selection point voltage Vs and the non-selection point voltage Vus are selected to be a voltage "2" below this threshold voltage V th . Iro, V t b =
When 1.7v and u=64 trees, ■-16,6■ are obtained, and when N=128 trees with the same intercolor, V=19.
2■ is obtained.

FIG. 4 shows a -deformed structure of the liquid crystal display spring /l' (18). In the above example, the signals A and B are both displayed in the same dark color, but in this modification, they can be displayed in different colors. That is, the signal lines Y of the liquid crystal display panel 08) are provided to face alternately red and black color polarizing plates 09). In this way, for example, signal A will be displayed in red and signal B will be displayed in black, making their distinction clear. In the figure, (21) is a transparent glass substrate, (221 is an X-side electrode made of an interlayer transparent conductive film such as an ITO film, (23) is also a Y-side electrode made of a TO film, etc., (24) ) (25) is a liquid crystal alignment film, (a) is a liquid crystal, and (b) is a reflective polarizing plate.

As described above, the memory scope of the present invention receives two types of signals:
By alternately applying signal lines to each tree, two types of waveforms are superimposed on the same screen or displayed on the same screen. Furthermore, since different types of displays can be displayed in different colors, they can be easily distinguished and there is no risk of erroneous reading during use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
) is a front view of the image showing the display state, Figure 6 is a signal waveform diagram,
FIG. 4 is a sectional view of the liquid crystal display panel. (1)...Switching on - Char, (2)...
・Amplifier, (3)...A/D converter, (4)・
...Memo! J, (5)...Trigger circuit, (61...Counter, (7+...-)
Memory write address counter, (8)...Multiplexer, +9)...Memory read address counter, no)...-number configuration circuit, (121
)(12z)(151)(152)--Shift register, (1η...display changeover switch, shout...
・Matrix display panel, (1g!...Color polarizing plate, (2))...Liquid crystal. 4th Figure 27~ Knee -522
−

Claims (1)

[Claims] 11. In a memory scope including a matrix display panel consisting of a plurality of scanning lines X and signal lines Y, a memory for alternately inputting and storing two types of signals, and extracting the two types of signals from this memory. a shift register that supplies two types of signals to every other signal line among the signal lines, a two-stage shift register that supplies scanning signals to the scanning line, a memory successive address counter that drives the two-stage shift register; A display changeover switch is provided to supply the output signals of the counters to the two-stage shift registers in series or in parallel.By switching this switch, when the two-stage shift registers are connected in series, two types of signals are displayed on the matrix display panel. A memory scope characterized in that when two-stage shift registers are connected in parallel, two types of signals are displayed on a display screen divided into two, respectively.