JPS59189799U - Erroneous insertion detection circuit in CMOSROM writing device - Google Patents
Erroneous insertion detection circuit in CMOSROM writing deviceInfo
- Publication number
- JPS59189799U JPS59189799U JP8392383U JP8392383U JPS59189799U JP S59189799 U JPS59189799 U JP S59189799U JP 8392383 U JP8392383 U JP 8392383U JP 8392383 U JP8392383 U JP 8392383U JP S59189799 U JPS59189799 U JP S59189799U
- Authority
- JP
- Japan
- Prior art keywords
- writing device
- erroneous insertion
- cmo3rom
- detection circuit
- cmosrom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は点対称な構造を持つＣＭＯ３ＲＯＭの外形の例
を示す図、第２図は本考案、による誤挿入検出回路の実
施例を示す回路図である。
Ｖｃｃ・・・・・・電源端子、Ｇ・・・・・・グランド
端子、Ｃ・・・・・・制御端子、Ｅ・・・・・・電源、
Ｒ・・・・・・保護抵抗、ＰＨ・・・・・・フォトカプ
ラ（電流検出素子） 、Ｓｌ、 Ｓ２． ｓ３゜Ｓ、・
・・・・・アナログスイッチ（スイッチング素子）、
・ＩＮＶ・・・・・・インバータ。FIG. 1 is a diagram showing an example of the external shape of a CMO3ROM having a point-symmetric structure, and FIG. 2 is a circuit diagram showing an embodiment of an erroneous insertion detection circuit according to the present invention. Vcc: power supply terminal, G: ground terminal, C: control terminal, E: power supply,
R...protective resistor, PH...photocoupler (current detection element), Sl, S2. s3゜S,・
...Analog switch (switching element),
・INV・・・Inverter.
Claims (1)
構造をしたＣＭＯ３ＲＯＭ書込装置の電源端子接続部と
グランド端子接続部との間にスイッチング素子および電
流検出端子を介して前記ＲＯＭに与える正規の電圧の数
分の−の電圧源を接続し、前記スイッチング素子を制御
することにより挿入されたＣＭＯ３ＲＯＭに正規の方向
および逆方向に前記数分の−の電圧を印加し、そのとき
電流が流れるかどうかを前記電流検出素子によって検出
することにより前記ＣＭＯ３ＲＯＭの誤挿入を検出する
ように構成したことを特徴とす′るＣＭＯ３ＲＯＭ書込
装置における誤挿入検出回路。A CMO3ROM writing device operates with a single power supply and has a structure in which the power supply terminal and the ground terminal are point symmetrical. By connecting a voltage source that is several times lower than the normal voltage and controlling the switching element, a voltage that is several times lower than the normal voltage is applied to the inserted CMO3ROM in the normal direction and in the opposite direction. An erroneous insertion detection circuit in a CMO3ROM writing device, characterized in that the erroneous insertion of the CMO3ROM is detected by detecting whether or not current flows by the current detection element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8392383U JPS59189799U (en) | 1983-06-03 | 1983-06-03 | Erroneous insertion detection circuit in CMOSROM writing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8392383U JPS59189799U (en) | 1983-06-03 | 1983-06-03 | Erroneous insertion detection circuit in CMOSROM writing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59189799U true JPS59189799U (en) | 1984-12-15 |
Family
ID=30213876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8392383U Pending JPS59189799U (en) | 1983-06-03 | 1983-06-03 | Erroneous insertion detection circuit in CMOSROM writing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59189799U (en) |
-
1983
- 1983-06-03 JP JP8392383U patent/JPS59189799U/en active Pending
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