JPS59189724A - Capacitor array type a/d converter - Google Patents

Abstract

PURPOSE:To improve the A/D conversion precision by constituting a capacitor array with a capacitor, which includes plural capacitors of minimum units, as a constitution unit to generate the value of the capacitor array with a high precision. CONSTITUTION:A capacitor CR where 4 capacitors whose one side has a length L are one constitution unit is shown in Fig. (1). Its capacity is 4L<2>XCox(F) and is equal to that of a conventional capacitor. When one of 4 capacitors is used for adjustment as shown in Fig. (2), the adjustment unit is L(mum)X1(mum)XCox(F/ mum<2>), and a capacitor Cs is generated with a precision twice as high as that of conventional unit 2XL(mum)X1(mum)XCox(F/mum<2>). With respect to the other C7-C0, integer-fold number of CRs are used as conventional, and for example, 8 CRs are used as C7 and 4 CRs are used as C6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-stage capacitor array type A/D converter, in which a capacitor array is constructed using a capacitor including a plurality of minimum unit capacitors as a constituent unit.
Regarding D converter. The conceptual diagram of the basic circuit configuration of the two-stage capacitor array type A/D converter (8btt) handled in this invention is shown in Figure 1. When the capacitance of the constituent unit capacitor is normalized to 1, each value is ' 7 (1
4)=8.0゜(15)=4 , a, (i 2)
=2,04(11)"1+'s(10)
= 8 w C2(9) = 4 e C5(8)=
2#0Rc7)tc@(6)=i wag(15)
=16/15. It is generally well known that the accuracy of a capacitor array type A/D converter is determined by the relative accuracy of the values of each capacitor. Here, in the integrated circuit, this A
/ When making a D converter, the problem is how to make these capacitors. However, C75C6s...
..., Oo, for OR, af~C1 is C8
, Considering that the capacity is an integral multiple of OR, C7 is OR
The following 06~c
Capacitors up to 1 can be easily made. However, Of+ is 16715 times the constituent unit, and A/D
It is difficult to make it because it greatly affects accuracy. An example of the structure of a capacitor in an integrated circuit is shown in FIG. 2 using AAl, gate oxide film 2. It is composed of three diffusion layers 3, and its capacitance is determined by the area of the gate oxide film 2. Therefore, when making 08, this area must be changed. In the conventional method [;! J3-(1) f1
As shown in Figure 3-(2), one side was adjusted by ΔL1/l m for 1 unit to make it 16/15. However, in general, this ΔL1 has to take a discrete value of 1 μm, 2 μm, and 1 (+) due to the pattern design aI of the integrated circuit. Therefore, the unit of adjustment of the value of C8 according to the conventional method is oox (F /μm2) is the gate capacitance per jltl plane, then 2I, (μm
) X 1 (/i m) X Oox (F/
μtn2).

In other words, for the OR of the constituent units, 2/LX100 (%)
All you can do is adjust the units. This will not be a problem if the length L of one side of the capacitor is large, but if the length L of the - side is small, only rough adjustment will be possible.
The accuracy of D deteriorates. Since the capacitor in an integrated circuit has an extremely large effrii product compared to other elements, it must be made as small as possible when designing the pattern. Therefore, adjusting C8 using the conventional method does not improve the precision of the A/D. It is clear that no improvement can be expected.

The present invention eliminates such drawbacks, and its purpose is to improve A/D conversion accuracy by creating the value of 01ll of the capacitor array with high accuracy.

The present invention will be described in detail below based on Examples.

FIG. 4-(1) shows a capacitor OR in which four capacitors each having a length L on the negative side form one structural unit. This capacity is 4L"X0ox(F), which is equal to the conventional one shown in FIG. ), one of the four capacitors is used for adjustment.The adjustment unit in this specific example is L(l1m)xl(μgn)
Oox(F/μrIL2), which is different from the conventional 2×L(
2 compared to
Capacitor 08 can be made with twice the precision. other C
0 to Co are the same as before, C1 is the same as OR, 8 pieces, C
6 may be used in integral multiples, such as 4 pieces. As a specific example of the present invention, a square capacitor with side L (μ, rL) is made the minimum unit, and four capacitors are combined to form a medium configuration, or by further reducing the capacitance of the minimum unit capacitor, By increasing the number of minimum unit capacitors per constituent unit, it is possible to make the adjustment on day 0 more fine.

According to the present invention, in a two-stage capacitor array type A/'D converter, the value of the capacitor C8 can be made more accurately than in the conventional method, and the effect on the A/D conversion accuracy is large.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of the original circuit configuration of a two-stage capacitor array type A/D converter. 1... Capacitor array... Comparator 3... Switch 4... Input voltage 5... Reference voltage 6... OR 7...C. 8...C1 9...C2 10...C3 11...C1 12...C11 16...C6 14. ...C7 15...C8 Figure 2 is a structural diagram of a capacitor in an integrated circuit 1...
. . . Aluminum 2 . . . Gate oxide film 6 . FIG. 3(2) is a diagram showing the shape of C8 according to the conventional method. FIG. 4(1) is a diagram showing a specific example of a structural unit according to the present invention. FIG. 4(2) is a diagram showing a specific example of the shape of the OB according to the present invention. In each figure, 1 indicates the size of the gate oxide film. Applicant: Shikiwa Seikosha Co., Ltd. 2

Claims (1)

[Claims] An integrated circuit two-stage capacitor array type A/D converter, characterized in that a capacitor array is constructed using a capacitor including a plurality of minimum unit capacitors as a constituent unit.