JPS59189651A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the insulating isolation among the electrodes as well as to extremely reduce the leakage current even at the operation with high temperature by using zirconium oxide for an insulating material to form the isolation region. CONSTITUTION:On a semi-insulating GaAs substrate 1, a buffer layer 2 and further on that an N type active layer 3 are epitaxially grown. A photoresist 8 is coated and patterning is done to expose the substrate surface 10 to become an insulating isolation region. Etching is done from the substrate surface 10 so far as etching proceeds into the buffer layer 2 and zirconium oxide 9 is stuck to the whole surface of the substrate so as to equalize its thickness to the depth of etching. Then the photoresist 8 and the zirconium oxide layer 9 on said photoresist 8 are removed by an organic solvent. After that, the heat treatment is performed in order to increase the tightness of the contact of the zirconium oxide layer 9 and the buffer layer 2. The electrodes such as a gate 4, a source 5 and a drain 6 are formed and each electrode is lead out on the zirconium oxide layer 9 and then the electrode pads are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device VC, and more particularly to a semiconductor device having a separate region for electrically isolating electrodes and elements.

The isolation region in the semiconductor device VC is separated by the distance k between the regions to be separated.
'm: Although it is important to electrically insulate VC, it is easy to insulate VC.
For example, PN junction isolation in integrated circuit devices can be easily formed by diffusing impurities into the substrate, but it is still a step forward in terms of insulation, and isolation The area occupied by the region also increases. Therefore, the idea of forming isolation regions using insulating materials such as oxide films has been reconsidered, and with recent developments in semiconductor device manufacturing technology, it has become easier to form isolation regions using insulating materials. Silicon oxide is often used as an insulating material from the viewpoint of heat resistance.

By the way, the operating current in the semiconductor device VC is becoming smaller and smaller due to lower power consumption and the like. For this reason, leakage current in semiconductor devices has become a problem in conventional semiconductor devices.

The operating current was so large that the leakage current was negligible, but as the operating current became smaller.

Leakage current can no longer be ignored. From this point of view, the isolation between elements using the aforementioned PN junction is insufficient, and isolation between elements using an insulating material is preferable. However, it has been found that the conventional isolation using silicon oxide VC is not sufficient for semiconductor devices whose operating current is very small. In particular, it was found that the higher the operating temperature, the more the insulation deteriorates and the leakage current increases. This is because the rate of decrease in insulation resistance of silicon oxide due to temperature rise VC is relatively large.

Will the non-inventor further consider isolation region VC using insulating material VC?
As a result, it was discovered that the insulation properties were further improved by using zirconium oxide as an insulating material. Zirconium oxide has high insulation resistance, and its rate of decrease due to temperature rise is small. In addition, using sputtering method
Zirconium oxide can be easily formed on the substrate. If such a separation region made of zirconium chloride is used, the characteristics of the semiconductor device will be further improved.

Hereinafter, embodiments of the present invention will be described in detail from Zenzuta Jvc.

FIG. 1 shows an embodiment of the present invention, in which a GaAs Schottky barrier gate FETvc is applied. First, as shown in FIG. 2 (a) VC, (100) crystal plane? 1013 on the main surface and -rb semi-insulating GaAs substrate 1
A buffer layer 2 having a carrier concentration of ~t 014 cm-3 and a thickness of 3 to 7 μm is further applied on top of the buffer layer 2 having a carrier concentration of gold of 0.5 to 1.5 μm.
n-type active layer 3 with a carrier concentration of 5 x 10"7 cm"-3, continuous V with a thickness of 5-0.9 μm
C epitaxially grows.Next, as shown in FIG. 1(b) I/C, VC and photoresist 8? The device operating area f is coated using normal phosphorography technology.
The substrate surface 10 is patterned to expose the insulation isolation region. At this time, the cross section of the substrate that will become the insulation isolation region is (
011) and (011) crystal planes VC.

Next, as shown in FIG. 1(C) VC, for example, sulfuric acid H28
04 and hydrogen peroxide solution H2U2 mixture, Nokutsu 7A layer 2
until it penetrates approximately 2000-3000λ into the substrate surface 1.
Etching is performed from zero, and zirconium oxide is deposited on the entire surface by the snot-cutting VC method to a thickness equal to the etching depth, as shown in FIG. 1(d).

Then, as shown in FIG.
A so-called lift-off process is performed to remove the carbon by dissolving the organic material.

After that, the adhesion between the zirconium oxide layer 9 and the buffer layer 2 was completely increased.
Heat treatment is performed under two gas or inert gas (Ar, N2) atmosphere.

Next, as shown in FIG. 1(f), the gate 4. Source 5. An electrode for the drain 6 is formed, and a VC lead electrode pad is formed on each electrode yas-ized zirconium layer 9.

According to VC, non-invention as explained in detail above.

The use of a highly insulative fermented zirconium layer enables insulation separation between electrodes, resulting in extremely low leakage current even during high-temperature operation. Since the surface of the insulating layer 9 and the surface of the active layer 3 are at the same height, the surface of the element is flattened and there is an effect that disconnection of the electrode wiring does not occur.

Note that the present invention can be applied not only to discrete VC but also to IC inter-element isolation VC, and the substrate material may be GaA.
Other semiconductor materials besides s are also possible.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are cross-sectional views showing an embodiment of the present invention in the order of steps. 1...Semi-insulating GaAs substrate, 2...
...Nokutufa layer, 3...n-type active layer, 4...
・Gate, 5--Source, 6--Drain, 7--Mesa step, 8--Photoresist, 9--Zirconium oxide, 10...
...Surface of the board. -1□ノ

Claims (1)

[Claims] In a semiconductor device VC in which the isolation region is entirely formed with an insulating material,
A semiconductor device characterized in that the insulating material VC# zirconium is completely used.