JPS59189425A - Data processing device - Google Patents

Abstract

PURPOSE:To make the adjustment for every product unnecessary by detecting a phase error between observation points by a storage element, varying a delayed quantity of a variable delay element so that the error is corrected to an allowable value or below, and executing a clock phase adjustment. CONSTITUTION:A waveform observation point TP1 is connected to storage elements F0-F3 through a delay element DL3, and an observation point TP2 is connected to the storage elements F0-F3 through delay elements DL4-7. The delay elements DL3-7 have a delay quantity of 3alpha, 0, 2alpha, 4alpha, and 6alpha, respectively. A reference timing clock is generated from a clock of the observation point TP2, a clock of the observation point TP1 is sampled, and from the contents of the storage elements F0-F3, a phase correction controlling circuit 9 decides a phase error, outputs correcting signals 10, 11, changes a delayed value of variable delay elements DL1-2, corrects a phase, and sets the phase error to an allowable value or below. In this way, the phase adjustment is executed automatically, and the test adjusting time is reduced.

Description

[Detailed Description of the Invention] - [Technical Field of the Invention] The present invention relates to a data processing device, and relates to a clock phase adjustment for providing required specifications and a clock to the clock input terminal of each storage element of the data processing device. be.

[Prior art]

In general, in data processing devices, the clock supply path from the clock generation source to the clock input terminal of the storage element has delay elements with different delay values depending on the path, and furthermore, this delay value has variations due to manufacturing. There is. Therefore, in order to provide a clock consistent with the required specifications to the clock input terminal of each storage element, it is necessary to make adjustments for each product.

Conventionally, as a clock phase adjustment method, a variable delay element is provided for each clock supply path, and the phase error is eliminated by adjusting the variable delay element while observing the clock waveform given to the storage element through each supply path with an oscilloscope. There was a way to keep it below the allowable value.

FIG. 1 shows an example of how to implement the conventional method, in which the same clock is applied to two storage elements through separate paths.

In the figure, (1-1) is a clock supply circuit, (2) is a clock generator, (3) and (4) are the first and second storage elements, respectively, and (5) and (6) are the first and second storage elements, respectively.
and a clock supply path to the second storage element, (7)
, (8) are the clock supply paths (5) and (6), respectively.
), (TPI) and (TP2) are the waveform observation points of the clock input to the first and second storage elements (3) and (4), respectively. 1
), (DBP) are the clock supply path (5), respectively.
(6) is a variable delay element for adjusting the phase of the clock output to the clock supply circuit (6), and (CT1) and (CT2) respectively indicate output terminals from the clock supply circuit (1).

In this circuit, the delay elements (7) and (8
) have different delay values, the waveform observation point (TPl),
The clock waveform at (TP2) was observed with an oscilloscope, and the clock phase error was kept below the allowable value by adjusting the variable delay elements (DLl) and (DBP).

Since clock phase adjustment in conventional data processing devices is performed as described above, adjustment is required for each product. In addition, the number of points to be evaluated and the number of adjustment points (...) are large, and the number increases as high performance is required, and there are drawbacks such as a long adjustment time.

[Summary of the invention]

This invention was made with the aim of improving this drawback, and it is possible to automatically adjust the clock phase by detecting the phase error between each observation point and correcting the error to below the allowable value based on the result. The present invention provides a data processing device that does not require adjustment.

[Embodiments of the invention]

An embodiment of the present invention shown in FIG. 2 will be described below. In the figure, (2-1) is a clock supply circuit with an automatic phase correction function, (2) is a clock generator, and the clock whose antiphase is adjusted by variable delay elements (DLl) and (DBP) is output from the output terminal ( CT1) and (CT2) are output to the clock supply path. ' Also, (DLR) (
DL4), (DL5), (DL6), (DL7)
is the observation point (TP 1).

(6α, 0, 2α, and 4α for the timing generation delay elements for detecting the magnitude of the phase error of TP2>, respectively.

FO, Fl, F2. with a delay value of 6α. F3 is the output data input of delay element DL3, and delay element DL4. DL5. DL6. A memory element whose clock input is the output of DL7, (9) is a memory element FO, Fl,
F2. A correction control circuit that determines a phase error from the output of F3 and outputs a phase correction signal, αq and α°C are variable delay elements DL1. This is a phase correction signal for correcting the phase by changing the delay value of DL2.

Figure 6 shows observation point TP2, delay element DT, and 4°DL.
5. DL6. It is a timing chart of the output waveform of DL7.

Figure 4 shows that the clock phase of observation point TPI is the same as observation point T.
When the phase at P2 is delayed by +6α, the content of the memory element is (FO.

Fl, F2. Fro) = (0,'0.0.' 1)
becomes.

FIG. 5 shows the principle of clock phase error detection and correction in this example. When the clock phase at observation point TP2 is a reference value (0) and the clock phase at observation point TP1 is represented by G, storage elements FO, Fl.

F2. For all cases of the contents of F, the thickness of G and the effect of the phase correction signal -, αη at that time are shown.

Next, the operation will be explained. Two clock phase observation points TP1. In the clock supply circuit located at the same distance from TP2, the reference timing is calculated from the clock at observation point TP2.
By creating a taro clock and using the clock of observation point TPI as a sample, storage elements FO, F1. F2. The correction control circuit (9) determines the phase error from the contents of 'F' and outputs a phase correction signal. Variable delay element DL1. DL2 changes the delay value according to the phase correction signal, and corrects the clock phase error so that it is less than the allowable value.

As a specific example, the case shown in the timing chart of FIG. 4 corresponds to case (2) in FIG. 5, and the correction control circuit (9)
A phase correction signal - for reducing the delay value of variable delay element DL1 by 2α is outputted from DL1, and as a result, the phase error becomes less than the allowable value ±α.

In addition, to explain case 1 in FIG. 5, the memory element FO
, Fl, F2. It is determined from the contents of F3 that the error value G is larger than 6α, and the phase correction signal α acts to increase the delay value of the variable delay element DL1 by 6α. When this correction result becomes case 1 again, the above operation is repeated, and eventually case 2. Either case 6' or case 4 will be the case. Here, in case 2 or case 4, further correction is performed, and when case 6 is reached, the correction is completed.

In addition, in the above example, the case where there are two observation points and error detection is performed using one of the clock phases at the observation points as the reference phase, but the number of observation points may be any number, and the reference clock phase for error detection may be used as the reference phase. may be used other than observation points. Furthermore, as the number of observation points increases, the hardware for error detection and correction control becomes large, so a system may be used in which a circuit for selecting observation points is provided and correction is performed in order. Further, the mathematical expressions for the delay values and the like in this embodiment may be changed depending on the correction accuracy and the like.

〔Effect of the invention〕

As described above, according to the present invention, since the clock phase is automatically adjusted, the test yH adjustment time of the device can be reduced, and a high IIv variation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of conventional clock phase adjustment in a data processing device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a timing chart of the reference clock in FIG. FIG. 4 is a timing chart showing examples of waveforms observed in the embodiment, and FIG. 5 is an explanatory diagram showing the operating principle in the embodiment. In the figure, (2-1) is a clock supply circuit. FD, Fl, F2. F3 is a storage element, (9) is a correction control line, DL1. DL2 is a variable delay element, DL3 to DL
7 is a slow W element. The same symbols in the figures are the same (
indicates a considerable portion. Agent Masuo Oiwa Figure 3 Figure 4 Figure 5 U θ Procedural amendment (voluntary) Showa 5% 5,17 8 2. Name of the invention Data processing device 3. Person making the amendment Relationship to the case Patent applicant residence Address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, coffin of "Detailed Description of the Invention" in the agent's specification. 66 Contents of amendment 127

Claims (1)

[Claims] A correction control circuit which is supplied with the output signal of the storage element, detects the phase error of the clock from the output signal and generates a phase correction signal, and generates a clock by changing the delay value of the variable delay element according to the phase correction signal. 1. A data processing device, characterized in that the phase of an output clock of the device is adjusted to control the phase error of the clock to a predetermined value.