JPH11242530A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent noise caused by the control clock signal of a digital signal circuit-side from being loaded on the power of an analog signal sampling circuit at the time of sampling the analog signal in the analog signal sampling circuit. SOLUTION: This signal processor is provided with a delay circuit 15 controlling delay time from outside. Delay is generated in mutual timings in the control clock signal DCLK of a digital signal circuit 14 side and the sampling control clock signal CTCLK of an analog signal sampling circuit 13 side and a phase is changed. Thus, noise caused by the control clock signal DCLK of a digital signal circuit 14 is prevented from being loaded on the analog signal sampling circuit 13-side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal processing apparatus applied to a semiconductor integrated circuit provided with a digital signal circuit and an analog signal sampling circuit each controlled by a clock signal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a circuit configuration of a conventional signal processing device. Reference numeral 21 denotes a first clock generation circuit, 22 denotes a second clock generation circuit, and 23 denotes a first clock generation circuit 21. A digital signal circuit 24 is controlled by a clock signal DCLK from the second clock generator, and an analog signal sampling circuit 24 performs a sampling process by the clock signal ACLK from the second clock generation circuit 22.

As shown in FIG. 4, a clock signal CLK externally supplied from a CLK terminal 25 is supplied to a first clock generation circuit 21 and a second clock generation circuit 22.
, And the first clock generation circuit 21 generates the clock signal DCLK, and the second clock generation circuit 22 generates the clock signal ACLK. Then, the clock signal DCLK generated by the first clock generation circuit 21 is supplied to a digital signal circuit 23, and the digital signal circuit 23 controls the digital signal DIN input from the DIN terminal 26.

On the other hand, the clock signal ACLK generated by the second clock generation circuit 22 is supplied to an analog signal sampling circuit 24, which samples the analog signal AIN input from the AIN terminal 27. I do.

At this time, there is no phase difference between the clock signal DCLK generated by the first clock generation circuit 21 and the clock signal ACLK generated by the second clock generation circuit 22. That is, the analog signal sampling circuit 2
When the sampling of the analog signal AIN is performed in step 4, the signal control is also performed in the digital signal circuit 23.

[0006]

In the prior art, noise generated in synchronization with the control clock signal DCLK on the digital signal circuit 23 side is generated by a power supply line or a signal line on the analog signal sampling circuit 24 side. In the analog signal sampling circuit 24 at the time of data sampling for the analog signal AIN.

FIG. 5 is a timing chart of each signal for explaining a state in which the noise is present in the conventional circuit configuration shown in FIG. 4, and shows the clock signal CLK and the waveforms of the clock signals DCLK and ACLK. It has become. FIG. 5 shows a state in which noise N is present in the waveform of an applied voltage AVDD of an analog power supply (not shown) applied to the circuit. In the waveform of the analog signal AIN input from the outside, As in the case of analog signal data sampling (Sampling
1,...), The noise N from the analog power supply is loaded.

As described above, the conventional circuit configuration has a problem that the characteristics of the analog signal sampling circuit 24 are deteriorated due to the influence of the noise N from the digital signal circuit 23 side.

In view of the above, the present invention solves the above-mentioned conventional problems and provides a method for controlling the timing of a clock signal for control on the digital signal circuit side and the timing of a clock signal for sampling control on the analog signal sampling circuit side. The object of the present invention is to provide a signal processing device which can adjust the analog signal sampling circuit so as to have the most appropriate sampling timing according to a method of use or an external condition, thereby enabling more accurate signal processing. It is assumed that.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for generating a control clock signal for a digital signal circuit and a control clock signal for an analog signal sampling circuit from an external clock. A circuit for delaying the clock signal for controlling the circuit so as to have a phase difference with respect to the clock signal for controlling the digital signal circuit is provided, and the delay time can be externally controlled to an optimum delay time. To do.

[0011] For this reason, it is possible to cause a difference in the timing of the control clock signal between the analog signal sampling circuit and the digital signal circuit, so that noise synchronized with the timing of the control clock signal for the digital signal circuit is reduced. It is possible to avoid being loaded during sampling on the analog signal sampling circuit side, so that the characteristics of the analog signal sampling circuit are remarkably improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a digital signal circuit and an analog signal sampling circuit respectively controlled by a clock signal, and the analog signal sampling circuit for controlling the digital signal circuit. A delay circuit for generating a phase difference in the clock signal of the signal sampling circuit; and this configuration causes a difference in the timing of each control clock signal between the analog signal sampling circuit and the digital signal circuit. Therefore, when signal processing is performed in the digital signal circuit, signal sampling is not performed in the analog signal sampling circuit.
That is, the analog data is sampled when there is no noise due to the digital circuit control clock on the analog power supply. Therefore, it is possible to prevent the noise synchronized with the timing of the clock signal for controlling the digital signal circuit and the same level signal from being introduced at the time of sampling on the analog signal sampling circuit side.

According to a second aspect of the present invention, the delay time of the delay circuit can be set from the outside. With this configuration, the delay time can be externally controlled to an optimum delay time.

According to a third aspect of the present invention, there is provided a measuring circuit for measuring a characteristic of the analog signal sampling circuit, wherein a delay time of the delay circuit is adjustable so as to obtain a predetermined characteristic. Thus, it is possible to adjust the analog signal sampling circuit in an actual operation state so that the circuit characteristic becomes a preset characteristic.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a signal processing device for explaining a first embodiment of the present invention.
Reference numeral 11 denotes a first clock generation circuit,
A basic clock signal CLK is input from the K terminal 16. Reference numeral 12 denotes a second clock generation circuit, to which a clock signal CLK is input from a CLK terminal 16 as described above. Reference numeral 14 denotes a digital signal circuit, which is configured so that the digital signal DIN input from the DIN terminal 17 is controlled by the clock signal DCLK generated by the first clock generation circuit 11.

Reference numeral 13 denotes an analog signal sampling circuit, which is an analog signal AI input from an AIN terminal 18.
N is input. The clock signal ACLK generated by the second clock generation circuit 12 is
The signal is input to the delay circuit 15.
The output of the delay circuit 15 is input to the analog signal sampling circuit 13. The analog signal sampling clock signal CT generated and output by the delay circuit 15
The configuration is such that the analog signal AIN is sampled by CLK.

The delay circuit 15 is connected to a CTL terminal 19 so that the delay time can be externally controlled, and optimally adjusts the delay time by a control signal CTL input from the CTL terminal 19 from the outside. It is configured to be able to.

FIG. 2 is a timing chart of the signals in the circuit configuration of FIG. 1. In FIG. 2, the analog signal AIN input from the AIN terminal 18 is subjected to data sampling by the rising edge of the analog signal sampling clock signal CTCLK. (Sampling
1,...). Here, the clock signal ACLK generated by the second clock generation circuit 12
Has the same phase as the clock signal DCLK generated by the first clock generation circuit 11, but the analog signal sampling clock signal CTCLK is set from the outside and CTL
The clock signal DC for controlling the digital circuit is delayed by the control signal CTL input from the terminal 19.
Therefore, the noise N in the applied voltage AVDD of the analog power supply (not shown) applied to the circuit does not appear at the time of analog signal sampling (Sampling 1,...).

That is, when signal processing is performed in the digital signal circuit 14, no signal is sampled in the analog signal sampling circuit 13, and a clock signal D for controlling the digital signal circuit is supplied to the analog power supply.
When the noise N due to CLK is not present, sampling of the analog signal is performed.

FIG. 3 is a block diagram showing a circuit configuration of a signal processing device for explaining a second embodiment of the present invention.
The basic configuration of the second embodiment is the same as that of the first embodiment, and the same members are denoted by the same reference numerals and detailed description is omitted. However, the second embodiment is different from the first embodiment. Has a configuration in which the analog output signal AOUT sampled by the analog signal sampling circuit 13 is input to the characteristic measuring circuit 20 in the same manner as in the first embodiment.

Further, the characteristic measuring circuit 20 includes a delay circuit 15
CTL terminal 19 is connected. Then, the feedback value is fed back to the control signal CTL of the delay circuit 15 so that the delay value can be changed based on the output AADJ of the characteristic measuring circuit 20, and the optimum delay value is set in advance in the analog signal sampling circuit 13. It can be set to have circuit characteristics.

As described above, since the delay time of the delay circuit 15 can be controlled so that the sampling output result of the analog signal sampling circuit 13 becomes the best, a clock for controlling the digital signal circuit 14 is used at the time of analog signal sampling. Since the signal DCLK and the analog signal sampling clock signal CTCLK can be reliably prevented from being synchronized, it is possible to obtain good circuit characteristics in which noise of the analog power supply does not enter during sampling.

In the above-described embodiment, a configuration having one digital signal circuit control clock signal and one analog signal sampling control clock signal has been described. The present invention can also be applied to the present invention, and the same operation and effect as described above can be obtained.

[0025]

As described above, according to the present invention,
When signal processing is performed in the digital signal circuit, signal sampling is not performed in the analog signal sampling circuit, and analog data sampling is performed when there is no noise due to the clock signal for digital circuit control on the analog power supply. Therefore, it is possible to prevent noise due to the clock signal for controlling the digital signal circuit from being loaded on the analog signal sampling circuit side, and it is possible to provide a signal processing device with remarkably high sampling accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a signal processing device for explaining a first embodiment of the present invention;

FIG. 2 is a timing chart of each signal in the circuit configuration of FIG. 1;

FIG. 3 is a block diagram showing a circuit configuration of a signal processing device for explaining a second embodiment of the present invention;

FIG. 4 is a block diagram showing a circuit configuration of a conventional signal processing device.

FIG. 5 is a timing chart for explaining a state where noise is present in the circuit configuration of FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 1st clock generation circuit 12 2nd clock generation circuit 13 Analog signal sampling circuit 14 Digital signal circuit 15 Delay circuit 16 CLK terminal to which a clock signal is inputted from the outside 17 DIN terminal to which a digital signal is inputted 18 Analog signal is inputted AIN terminal 19 CTL terminal to which delay time control signal is input 20 Characteristic measuring circuit CLK Basic clock signal CTL Delay time control signal AIN Analog signal DCLK Control clock signal generated by first clock generation circuit ACLK Control clock signal generated by the second clock generation circuit CTCLK Analog signal sampling clock signal AVDD Power supply voltage AOUT Analog output signal of analog signal sampling circuit AADJ Characteristic measurement Road output

Claims (3)

[Claims] 1. A digital signal circuit and an analog signal sampling circuit respectively controlled by a clock signal, and a delay circuit for generating a phase difference between the clock signal for controlling the digital signal circuit and the clock signal of the analog signal sampling circuit. A signal processing device comprising: 2. The signal processing apparatus according to claim 1, wherein a delay time of said delay circuit can be set from outside. 3. A signal according to claim 2, further comprising a measuring circuit for measuring a characteristic of said analog signal sampling circuit, wherein a delay time of said delay circuit is adjustable so as to obtain a predetermined characteristic. Processing equipment.