JPS59188930A - Tester - Google Patents

Tester

Info

Publication number
JPS59188930A
JPS59188930A JP6316383A JP6316383A JPS59188930A JP S59188930 A JPS59188930 A JP S59188930A JP 6316383 A JP6316383 A JP 6316383A JP 6316383 A JP6316383 A JP 6316383A JP S59188930 A JPS59188930 A JP S59188930A
Authority
JP
Japan
Prior art keywords
insulator
tester
terminals
electrodes
inspection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6316383A
Other languages
Japanese (ja)
Inventor
Sadao Matai
又井 定男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6316383A priority Critical patent/JPS59188930A/en
Publication of JPS59188930A publication Critical patent/JPS59188930A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable to measure an IC without using a probe card and a prober by a method wherein a device connected between both the terminals thereof with conductive layers in an insulating substrate is used, whose respective edges on one side are the connecting terminals with the electrodes of the IC, and the edges on another side are the connecting terminals to an IC tester. CONSTITUTION:An IC8 on a wafer 9 has Au electrodes 7, and the ceramics 11 of a tester 10 has electrode terminals 5 corresponding to the electrodes 7. The terminals 5 are connected to connecting terminals 4 to be connected to a tester table 2 according to Au layers 12. When the terminals 4 are made to come in contact with the connecting pins 6 of the tester base 2, the electric characteristic of the IC8 can be measured with favorable precision without necessitating a probe card, a prober and a connecting cable 3. Leads 20, etc. are annexed for making contact between the device 10 and the tester base 2, and when the IC is the specified IC, a circuit element is mounted in the device 10 or provided in the insulator 11. Or by providing a resistance layer in the insulator 11, or by flowing a liquid N2 in open hole parts, measurement of the characteristic of the IC8 can be performed also at a high temperature or at a low temperature.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置(以後ICと呼ぶ)の電気
特性の測定を行なうための検査装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection device for measuring electrical characteristics of a semiconductor integrated circuit device (hereinafter referred to as an IC).

ICの製造工程において半導体集積回路装置基板(以後
ウェノ・−と呼ぶ)上に形成されたICの電気特性全測
定するため、ウエノ1−を間欠送りする装置(以後プロ
ーバと呼ぶ)により間欠送りさレタウェハーをICテス
ターによ、9ICのit気特性を測定する。この時プロ
ーバにはICテスターとIC間を接続するため[ICの
電憔に対応した探針を絶縁基板に固定したグローブカー
ドと呼ばれる物を一般に使用している・ しかしICの電極は通常的100μm角の大きさからな
ジ、かつICの機能向上によシミ億の数は増大する一途
である。このためICの電極に多数の探針金精要よく接
触させることが困難である〇あるいはICテスターとプ
ローブカード間の接続にはクープルによって接続δれて
いるため外部のノイズを受は精度よ<ICの測定を行な
うことが難しい。又、プローブカードの探針とICの電
極の相対的な位置合わせはプローバによって行なわれる
が、この時の位置合わせ全精度工く曾わせることは制度
な技術が必要とされ、かつ最近の全自動プローバに対し
てはICの測定結果の処理も行なわせようとする傾向が
ある。
In order to measure all the electrical characteristics of an IC formed on a semiconductor integrated circuit device substrate (hereinafter referred to as ``WENO'') during the IC manufacturing process, the UENO 1- is intermittently fed by a device (hereinafter referred to as a prober). The temperature characteristics of 9 ICs are measured using an IC tester on the wafer. At this time, in order to connect between the IC tester and the IC, the prober generally uses something called a globe card, which has a probe compatible with the IC's voltage fixed to an insulating substrate. However, the electrodes of the IC are usually 100 μm thick. The number of stains continues to increase due to the size of the corners and improvements in the functionality of ICs. For this reason, it is difficult to make precise contact with a large number of probe wires to the electrodes of the IC.Also, since the connection between the IC tester and the probe card is made by a couple, the external noise may be received and the accuracy may be affected. It is difficult to perform IC measurements. In addition, the relative positioning of the probe card probe and the IC electrode is performed using a prober, but achieving full precision positioning at this time requires a systematic technology, and recent advances in There is a tendency to have automatic probers also process IC measurement results.

このようにグローブカード及びプローバは年々尚裳な技
術が要求されており、膨大な開発費用が必要とされてい
る。又、プローバにおいては設置面積も1台につき約2
−必要で多大な設置面が必要である。
As described above, glove cards and probers are required to have more sophisticated technology year by year, and a huge amount of development costs are required. In addition, the installation area for each prober is approximately 2
- Requires a large amount of installation surface.

しかるに本発明によると、絶縁基板中の一端がICの電
悌と接触するための端子と一端がICテスターと接続す
るための端子とを有し、前記端子間?導電層により形成
されているIC検金装置が得られる。かかる装置を用い
ることにより従来のIC測定に便われていたグローブカ
ード、プローバを全く必要としないICの測定が可能と
なる。
However, according to the present invention, one end of the insulating substrate has a terminal for contacting the IC tester, and the other end has a terminal for connecting to the IC tester, and between the terminals? An IC inspection device formed of a conductive layer is obtained. By using such a device, it becomes possible to measure ICs without the need for a glove card or a prober, which have been used in conventional IC measurements.

つまり前記に示したようなグローブカードの位置合わせ
及びケーブル上のノイズの問題が解決されるだけでなく
、プローバのコスト並びにプロー)(の設置面積も不要
となるのである。
In other words, not only the above-mentioned problems of positioning the glove card and noise on the cable are solved, but also the cost and installation area of the prober are eliminated.

又、本発明を用いることによりICの電気特性の測定結
果不良品のICE対してマーキングを行なっていたが、
このマーキングも不要となる。つまクウェハー上の良品
と不良品のIC位置を記憶させ、ICのマウント工程に
おいて自動的に良品のI’Cのみ全マウントする方法が
行なえるようになる。
Furthermore, by using the present invention, marking was performed on ICEs that were found to be defective as a result of measuring the electrical characteristics of ICs.
This marking is also unnecessary. It becomes possible to memorize the positions of good and defective ICs on the wafer and automatically mount all the good IC's in the IC mounting process.

以下本発明の実施例を図面管用いて説明する。Embodiments of the present invention will be described below with reference to drawings.

第1図は本発明の検査装置10を用いてICの電気特性
を測定している様子を表わした概略図である。第2図か
ら5g8図まではいづれも本発明の検査装置tlOの断
面図である。先づ第1図(2)は本発明の検査装置10
をテスターステーション2に設置しICテスター1によ
りICの電気特性を測定している様子ヲ表わし、第1図
(81ではテスターステーション2からウェハー9まで
の接続の様子を表わしている図である。
FIG. 1 is a schematic diagram showing how the electrical characteristics of an IC are measured using the inspection apparatus 10 of the present invention. 2 to 5g8 are all cross-sectional views of the inspection apparatus tlO of the present invention. First, FIG. 1 (2) shows the inspection device 10 of the present invention.
FIG. 1 (81) shows the state of connection from the tester station 2 to the wafer 9.

仄に第2図を用いて検査装置10の接続の様子をさらに
詳しく説明する。ウエノ・−9上に形成されたIC8の
電極7はアルミニウム又は金の材質からなる電極7全形
成しておく。一方検食装置10の絶縁体11ばたとえば
セラミックあるいはアルミナ、石英等からなる絶縁体1
1でIC8の電極7に対応した導電性の電極用端子5全
有し、この電極用端子5より導電層12によシテスター
ステーション2と接続するためのテスター用端子4を形
成する。前記4亀層2の形成する技術には蒸層法、プリ
ント法、低温焼結法等によシ金、銀、)くラジウム等の
導電性材料で4電層を形成するO前記検査装置10とテ
ストステーション2とを接続させるためには第1図(B
)に示すコンタクトピンbをテストステーション2側に
設置する必要がアク、このコンタクトピンbとテスター
用端子4を接触させれば良い。つま9ウエハー9上のI
C8の電極7よジ検食装置10全通してテストステーシ
ョン2に接続されるため従来使用していたグローブカー
ドとプローバ並びにこれらを接続していたケーブルも不
要となることからIC8の電気特性が精度良く測定する
ことが可能であるO第3図、第4図は検査装置10とテ
ストステーション2を接触させるためのテスタ一端子4
からのリード20,30の形状を表わしたものでめクチ
ストステーション2側にはリード20.30と全接続す
るためのソケットが必要である。このソケットはリード
20.30が接触した後に締め付けできる機構’tNし
ていることが望しいO第5図と第6図はIC8の′i[
、気特性を測定する場合、特定のIC8によっては回路
菓子4oを必要とすることがらシ、これらの回路索子4
(l横食装置10に実装又は絶縁体ll中に形成した検
査装置lOを表わす。
The manner of connection of the inspection device 10 will be explained in more detail with reference to FIG. The electrodes 7 of the IC8 formed on Ueno-9 are entirely made of aluminum or gold. On the other hand, the insulator 11 of the food inspection device 10 is made of, for example, ceramic, alumina, quartz, etc.
1 has all conductive electrode terminals 5 corresponding to the electrodes 7 of the IC 8, and a tester terminal 4 for connecting to the tester station 2 is formed from the electrode terminal 5 through a conductive layer 12. Techniques for forming the four conductive layers 2 include a vapor layer method, a printing method, a low-temperature sintering method, and the like. In order to connect test station 2 with
) It is necessary to install the contact pin b shown in FIG. I on toe 9 wafer 9
Since the C8's electrodes 7 and the food inspection device 10 are all connected to the test station 2, there is no need for the glove card and prober that were used in the past, as well as the cables that connected them. 3 and 4 show a tester terminal 4 for bringing the inspection device 10 into contact with the test station 2.
This figure shows the shape of the leads 20 and 30 from the top, and a socket is required on the client station 2 side to connect all the leads 20 and 30. It is desirable that this socket has a mechanism that allows it to be tightened after the lead 20.30 comes into contact.
, when measuring the characteristics, depending on the specific IC 8, a circuit wire 4o may be required.
(1 represents the inspection device 10 mounted on the side eating device 10 or formed in the insulator 11.

特に第6図においては回路菓子40を絶縁体ll中に形
成していることから第5図の検量装置lOの回路菓子4
0のよう7に収ジ付は位ftt−考慮する必要がない。
In particular, in FIG. 6, since the circuit confectionery 40 is formed in the insulator 11, the circuit confectionery 40 of the calibration device 10 in FIG.
There is no need to consider the digits ftt- for cases with a 7 such as 0.

第7図については検査装置10内の絶縁体11中に抵抗
層5θを形成し電流を印加することにより検査層tlO
とウェハー9を加熱させ、高温条件でのIC8の電気特
性を測定することができる。
Regarding FIG. 7, by forming a resistance layer 5θ in the insulator 11 in the inspection device 10 and applying a current, the inspection layer tlO
By heating the wafer 9, it is possible to measure the electrical characteristics of the IC 8 under high temperature conditions.

又、前記第7図の検査装置lOとは反対に低温条件での
電気特性全測定する場合は第8図の検査装置10のよう
に絶縁体11中に開穴部60を形成し、液体窒素又は液
体ヘリウム−#を流し込み検査装置10とウェハ−9全
低温条件にしてIC8の電気特性の測定を可能としたも
のである。
In contrast to the inspection device 10 shown in FIG. 7, when all electrical characteristics are to be measured under low temperature conditions, an opening 60 is formed in the insulator 11 as in the inspection device 10 shown in FIG. Alternatively, it is possible to measure the electrical characteristics of the IC 8 by pouring liquid helium # into the inspection device 10 and the wafer 9 under conditions of low temperature.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の検査装置を用いてICの電気特性の測
定をしている状態を表わす図である。第2図から第4図
はそれぞれ本発明の検査装置のテスター用端子とテスト
ステーションとを接触させるための構造の実施例を表わ
した図である。第5図と第6図はそれぞれ本発明の検査
装置に回路素子′に実装あるいは検査装置内に形成した
実施例′ft表わした図である。第7図と第8図はそn
ぞれ本発明の検査装置を高温あるいは低温下で使用する
ことを可6ヒとした実施例を表わした因である〇尚、図
において、1・・・・・・ICテスター、2・・・・・
・テストステーション、3・・・・・・ケーブル、4・
・・・・・テスター用端子、5・・・・・・電極用端子
、6・・・・・・コンタクトピン、7・・・・・・電極
、8・・・・・・IC,9・・・・・・ウェハー、10
・・・・・・検査装置、11・・・・・・絶縁体、12
・・・・・・導電層、20.30・・・・・・リード、
40・・・・・・回路菓子、50・・・・・・抵抗層、
60・・・・・・開穴部。 箭1区(B)
FIG. 1 is a diagram showing a state where the electrical characteristics of an IC are being measured using the testing device of the present invention. FIGS. 2 to 4 are views each showing an embodiment of a structure for bringing the tester terminal of the inspection device of the present invention into contact with the test station. FIGS. 5 and 6 are diagrams showing an embodiment of the present invention mounted on a circuit element or formed within the testing apparatus, respectively. Figures 7 and 8 are
This is because the test apparatus of the present invention can be used at high or low temperatures. In the figure, 1...IC tester, 2...・・・
・Test station, 3...Cable, 4・
...Tester terminal, 5...Electrode terminal, 6...Contact pin, 7...Electrode, 8...IC, 9. ...Wafer, 10
...Inspection device, 11...Insulator, 12
... Conductive layer, 20.30 ... Lead,
40...Circuit confectionery, 50...Resistance layer,
60...Open hole part. Yasu 1st Ward (B)

Claims (1)

【特許請求の範囲】 (1)ICの製造工程においてfcの電気特性を測定す
るための装置であって、絶縁体の一端にウェハー上に形
成されたICの電極に対応する複数の端子を有し、前記
端子よ勺導電層によシ絶縁体の他端でICテスターのス
テーションに対応する端子とを接続したことを特徴とす
る検査装置◎(り前記I’Cの電極に対応する複数の端
子はウェハー上の全ICの電極に対応していることを特
徴とする特許請求の範囲第(1)項記載の検査装置。 (3)前記ICテスターのステーションに対応する端子
に導電性のリードを形成したことを特徴とする特許請求
の範囲第(1)項記載の検査装置・(4) I Cの′
に気特性を測定するための回路素子を前記絶縁体の外壁
に形成したことを特徴とする特tff請氷の範囲1g 
(1)項記載の検査装置。 (5)高温条件でのICの′#L気特性を測定するため
の電気抵抗を有する材質前記絶縁体内に形成し電流を印
加することで加熱することができるようにしたことを特
徴とする特許請求の範囲第(1)項記載の検f装置。 (6)高温条件でのICの電気特性を測定するために前
記絶縁体に開穴部をMし液体窒素又は液体ヘリウム等を
注入できるようにしたことt%徴とする特許請求の範囲
第(r)項記載の検査装置。
[Scope of Claims] (1) A device for measuring the electrical characteristics of FC in the manufacturing process of IC, which has a plurality of terminals corresponding to the electrodes of the IC formed on the wafer at one end of the insulator. The test device is characterized in that the terminal is connected to the terminal corresponding to the station of the IC tester at the other end of the insulator through the conductive layer. The testing device according to claim 1, wherein the terminals correspond to the electrodes of all ICs on the wafer. (3) Conductive leads are attached to the terminals corresponding to the stations of the IC tester. The inspection device according to claim (1), characterized in that: (4) IC'
A special tff-applied area 1g characterized in that a circuit element for measuring the electrical properties of the insulator is formed on the outer wall of the insulator.
Inspection device described in (1). (5) A patent characterized in that a material having electrical resistance for measuring the characteristics of an IC under high temperature conditions is formed within the insulator and can be heated by applying an electric current. An f-detection device according to claim (1). (6) In order to measure the electrical characteristics of an IC under high temperature conditions, an opening is formed in the insulator so that liquid nitrogen, liquid helium, etc. can be injected into the insulator. Inspection device according to item r).
JP6316383A 1983-04-11 1983-04-11 Tester Pending JPS59188930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6316383A JPS59188930A (en) 1983-04-11 1983-04-11 Tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6316383A JPS59188930A (en) 1983-04-11 1983-04-11 Tester

Publications (1)

Publication Number Publication Date
JPS59188930A true JPS59188930A (en) 1984-10-26

Family

ID=13221294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6316383A Pending JPS59188930A (en) 1983-04-11 1983-04-11 Tester

Country Status (1)

Country Link
JP (1) JPS59188930A (en)

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