JPS59187457A - Method of polishing semiconductor base board - Google Patents

Method of polishing semiconductor base board

Info

Publication number
JPS59187457A
JPS59187457A JP58061783A JP6178383A JPS59187457A JP S59187457 A JPS59187457 A JP S59187457A JP 58061783 A JP58061783 A JP 58061783A JP 6178383 A JP6178383 A JP 6178383A JP S59187457 A JPS59187457 A JP S59187457A
Authority
JP
Japan
Prior art keywords
polishing
polish
pad
base board
abrasive grains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58061783A
Other languages
Japanese (ja)
Inventor
Akira Tabata
田畑 晃
Motomori Miyajima
基守 宮嶋
Yoshibumi Kikuchi
菊池 義文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58061783A priority Critical patent/JPS59187457A/en
Publication of JPS59187457A publication Critical patent/JPS59187457A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor

Abstract

PURPOSE:To polish the whole surface area of a base board to the same depth along the surface and at a high speed by adding abrasive grains smaller than a particular grain size into a polish liquid which is poured onto a rotating polish pad and uniformly separating by friction the separated-out Cu by means of said abrasive grain. CONSTITUTION:As for the types of abrasive grains, silicon carbide, alumina, silicon dioxide, etc. are used, and the grain size of less than 20mumphi or so, which inflicts less damage to the polishing surface while whose frictional effect is large, is desirable. The polishing is carried out, with the treated Si base board surface brought in contact with the face of a polish pad 6 which is being rotated at the number of revolution of 50 to 100r.p.m. and onto which a Cu plating polish liquid is poured at a rate of 2l/min. Thus, the Cu which is separated out on the polishing surface of the treated Si base board is separated from the Si surface by means of the friction with the abrasive grains contained in the polish liquid which is deposited on and rotated with the polish pad, thereby carrying out polishing at a high speed and to a uniform depth along the surface, without inflicting damage.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は半導体基板の研摩方法に係り、特に例えばそり
等により湾曲している半導体基板を、その湾曲面に沿っ
て高速で研摩する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of polishing a semiconductor substrate, and particularly to a method of polishing a semiconductor substrate that is curved due to warpage or the like at high speed along its curved surface.

(b)  従来技術と問題点 反り量の大きい半導体基板、例えばシリコン(St)基
板を、その表面に沿って一様な深さに研摩するに際して
は銅めりきポリッシング技術が用いられる0 この銅(Cu)めっきポリッシング技術というのは、硝
酸銅CLI(NO3)2とふり化アンモニウムNH,F
(多くは酸性ぶつ化アンモニウムNH4F−HFが用い
られる)を主成分とするポリッシング液(スラリー)を
Si基板面に注下し、下記反応式に示すようにSiを置
換して基板面に銅めっき層を析出させ、該Cuめっき層
をこすシ落とすこと姥よシ更にこの反応が繰シ返えされ
てSfのポリツシングが行われる公知の技術である。
(b) Conventional technology and problems When polishing a semiconductor substrate with a large amount of warpage, such as a silicon (St) substrate, to a uniform depth along its surface, copper plating polishing technology is used. Cu) plating polishing technology is copper nitrate CLI(NO3)2 and ammonium fluoride NH,F.
A polishing liquid (slurry) whose main component is acidic ammonium fluoride (NH4F-HF is often used) is poured onto the Si substrate surface, replacing Si as shown in the reaction formula below and copper plating the substrate surface. This is a known technique in which a layer is deposited, the Cu plating layer is scraped off, and this reaction is repeated to perform Sf polishing.

S i +2 Cu (NOs) 2 +4 NH4F
 →(NH4)2 S i F6+4 NH4N0 a
l2 Cuそして該Cuめつきポリッシングには通常の
片面研摩装置が用いられ、Cuめっきポリッシング(ス
ラリー)が注加されている回転研摩板即ちポリッシング
・パッド上にSi基板面をO〜80 [: f/crl
〕程度の圧力で接触させながら前記反応による化学研摩
がなされる。
S i +2 Cu (NOs) 2 +4 NH4F
→(NH4)2 S i F6+4 NH4N0 a
A normal single-sided polishing device is used for the Cu plating and polishing, and the Si substrate surface is polished at O~80 [: f /crl
] Chemical polishing is performed by the reaction while contacting with a pressure of about 100%.

しかしながら、例えば100[mmφ〕の基板で100
〜200〔μm〕程度の大きな反応を有するSi基板を
研摩する場合、基板面に沿って一様に研摩さtる性質を
有する上記Cuめっきポリッシング技術に於ても、81
面に析出したCuN4を剥離除去するだめの前記ポリッ
シング・パッドが一様に被研摩面に接触しないためにS
1面がそのそりに沿って一様に研摩されないという問題
を生じていた。
However, for example, a substrate with a diameter of 100 [mmφ]
When polishing a Si substrate that has a large reaction of about ~200 [μm], the Cu plating polishing technique described above has the property of polishing uniformly along the substrate surface.
S
A problem has arisen in that one surface is not polished uniformly along its warp.

即ちポリッシング・パッドの材料には通常ボリテクス等
と称されている2〜3〔關〕程度の合成皮革様のプラス
チック研摩郭成るいは2〜3(+n+++3程度のナイ
ロン短繊維が植えつけられたブラシ様のプラスチック研
摩布が用いられるが、例えば合成皮革様の研摩、布を用
いた場合基板の中心部が強く研摩布でこすられるために
基板の中央部が最も多く研摩され、又ブラシ様の研摩布
を用いた場合は、基板の圧接によって基板面に接するナ
イロン短繊維が倒れて基板面の中央部に対するスラリー
の供給が不充分になるために、基板面中央部の研摩量が
周辺部に比べて少くなるという問題を生ずる。
That is, the material of the polishing pad is usually a synthetic leather-like plastic abrasive pad of about 2 to 3 [m], called Voritex, etc., or a brush in which 2 to 3 (+n+++3) short nylon fibers are planted. For example, synthetic leather-like polishing, when cloth is used, the center of the board is rubbed strongly with the polishing cloth, so the center of the board is polished the most, and brush-like polishing When cloth is used, the short nylon fibers in contact with the substrate surface fall down due to pressure contact of the substrate, resulting in insufficient supply of slurry to the center of the substrate surface, so the amount of polishing at the center of the substrate surface is less than that at the periphery. This causes the problem that the amount of energy decreases.

この状態を示したのが第1図で、同図に於て(イ)は図
示したように合成皮革様ポリッシング・パッドPR上に
150〔μm〕程度のそりを有するSi基板Sを矢印の
ように圧接して従来のポリッシュ液を用いて研摩を行っ
た際の研摩量の面内分布を示したもので、同図(ロ)は
図示したようにブラシ様ポリッシング・パッドPB上で
(イ)同様にSi基板Sを従来のスリラーを用いて研摩
した際の研摩量の面内分布を示したものである。なおこ
こで使用した従来のCuめっきポリッシー液(スラリー
)はCu(N−03)2 : 500 (? 〕l N
H4F  HF : 2500(r)+H20:10[
A’)の混合溶液で、ポリッシング注加量2C1/=〕
、  ポリッシング・パッドの回転数80[r。
This state is shown in Figure 1, in which (a) shows a silicon substrate S having a warp of about 150 μm on a synthetic leather-like polishing pad PR as shown by the arrow. This figure shows the in-plane distribution of the polishing amount when polishing is performed using a conventional polishing liquid while pressing on the brush-like polishing pad PB. Similarly, it shows the in-plane distribution of the polishing amount when the Si substrate S was polished using a conventional chiller. The conventional Cu plating polish solution (slurry) used here was Cu(N-03)2:500(?]lN
H4F HF: 2500(r)+H20:10[
With the mixed solution of A'), polishing amount 2C1/=]
, polishing pad rotation speed 80 [r.

p9m]+基板圧接加重10 C9/ctl ’Jであ
る。
p9m]+substrate pressure contact load 10C9/ctl'J.

(C)  発明の目的 本発明の目的とするところは、上記問題点を除去し半導
体基板面をその表面形状に沿って均一に研摩することが
可能な銅めっき−ポリノシュ方法を提供することにある
(C) Purpose of the Invention The purpose of the present invention is to provide a copper plating-polinoche method that eliminates the above-mentioned problems and can uniformly polish a semiconductor substrate surface along its surface shape. .

(d)  発明の構成 即ち本発明は半導体基板の研摩方法に於て、回転するポ
リッシー・パッド上に硝酸銅とふっ化アンモニウムを主
成分とし、砥粒を含有せしめた銅めっきポリッシー液を
注下しつつ、該ポリッシュ・パッド面と半導体基板面を
接触せしめることにより該半導体基板面の化学研摩を行
うことを特徴とする。
(d) Structure of the Invention That is, the present invention is a semiconductor substrate polishing method in which a copper plating polishing solution containing abrasive grains and containing copper nitrate and ammonium fluoride as main components is poured onto a rotating polishing pad. At the same time, the semiconductor substrate surface is chemically polished by bringing the polish pad surface into contact with the semiconductor substrate surface.

(e+  発明の実施例 以下本発明を7実施例について、図を用いて詳細に説明
する○ 第2図は片面研摩装置の断面模式図で、第3図は本発明
の方法でシリコン基板の研摩を行った際の研摩量の面内
分布図である。
(e+ Embodiments of the Invention Below, seven embodiments of the present invention will be explained in detail with reference to figures.) Figure 2 is a schematic cross-sectional view of a single-sided polishing device, and Figure 3 is a method for polishing a silicon substrate by the method of the present invention. FIG. 4 is an in-plane distribution diagram of the amount of polishing when performing this process.

本発明の半導体基板の研摩方法に於ては、銅(Cu)め
っきボリッシー液として従来のCuめりきポリッシー液
10[[]に対して例えば50〜200〔2〕程度の該
ポリッシングに対して化学的に安定な砥粒を加えたポリ
ッシー液を使用する0砥粒の種類としては炭化珪素(S
in)、アルミナ(AA!203)を二酸化シリコン(
SiO2)等が用いられ、その粒度は摩擦効果が犬きく
、シかも被研摩面に与えるダメージの少ない20〔μm
φ〕以下程度が望ましい。本実施例に於ては、その組成
の一例としてCu(NQ、)。
In the method of polishing a semiconductor substrate of the present invention, a chemical polishing solution of about 50 to 200 [2] is used as a copper (Cu) plating polishing solution to the conventional Cu plating polishing solution 10 [[]. Silicon carbide (S
in), alumina (AA!203) and silicon dioxide (
SiO2) etc. are used, and the particle size is 20 [μm], which has the best friction effect and causes less damage to the polished surface.
φ] or less is desirable. In this example, Cu(NQ, ) is used as an example of the composition.

: 500Cry、NH41−HF: 2500[り:
L H2O: 1(7)の混合溶液に約100(r’)
の5iC(粒度0.06〜16〔μmφ〕)よシなる砥
粒を1屓させたCuめっきポリッシュ液を使用したO 又研摩装置としては、例えば第2図に模式的に示したよ
うな従来同様の片面研摩装置を使用する0なお同図に於
て、1は平板状回転テーブル、2はボリソシ=、・パッ
ド、3は被処理基板固持板、4は支軸兼ボリッシー液注
下管、5はサセプタ、6はSi被処理基板、7はボリッ
シー液注入矢印し、8はポリッシュ・パッドの回転を示
す矢印しである0 そして研摩に際しては50〜1001:r、p、m’l
程度の回転数で回転させたポリソシーφバッド2上に前
記本発明のCuめりきボリッシー液を2CIl/−i−
〕程度の量で注加しつつ、該ボリソシー・パッド上に被
処理Sl基板面を接触させて研摩を行う0本発明のポリ
ッシー液を用いた場合、被処理Si基板の被研摩面に析
出したCuは、ポリノシー・バット上に被着して回転し
ているポリッシングに含まれる砥粒による摩擦によって
Si面から剥離せしめられるので、被研摩Si面のボリ
ノシー・パッド上に接触する圧力は0〜io[f/ci
〕の範囲で充分である。又ポリノシー・パッドの材料と
しては、被研摩面に対するあたシがやわらかく、且つ多
量にボリッシー液を含むことができる前述したブラシ様
の研摩布を用いることがより望ましい0そして上記実施
例の方法に於ては、被研摩面の全域にわたって充分にポ
リ、シュ液の供給がなされ、且つ析出Cuが砥粒によっ
て一様に摩擦剥離されるので、第3図に示すように被研
摩面全域にわたってばらつきが101μm〕以下のほぼ
一様な研摩量の分布が得られる。なお該実施例に用いた
被処理Si基板は被研摩面側が凸面状に100〜200
(μm)程度そった1 00 〔mmφ〕の単結晶Si
基板で、該実施例に於て得られた研摩速度は15〔μm
/馴〕程度であった。
: 500Cry, NH41-HF: 2500Cry:
L H2O: Approximately 100 (r') in a mixed solution of 1 (7)
5iC (particle size: 0.06 to 16 [μmφ]) using a Cu plating polishing solution containing one scoop of abrasive grains. In the same figure, 1 is a flat rotary table, 2 is a polishing pad, 3 is a substrate holding plate to be processed, 4 is a support shaft and a polishing liquid injection pipe, 5 is the susceptor, 6 is the Si substrate to be processed, 7 is the Borisshi liquid injection arrow, and 8 is the arrow indicating the rotation of the polishing pad.0 And during polishing, 50 to 1001: r, p, m'l
The Cu-plated solution of the present invention was applied to the polysomatic φ pad 2 which was rotated at a rotational speed of about 2CIl/-i-.
When the polishing liquid of the present invention is used, polishing is carried out by bringing the surface of the Sl substrate to be processed onto the borisosy pad while adding the polishing liquid in an amount of about Since the Cu is peeled off from the Si surface by the friction caused by the abrasive grains contained in the rotating polishing material deposited on the polynosy pad, the pressure of the polished Si surface contacting the polynosy pad is 0 to io. [f/ci
] is sufficient. As the material for the polynosie pad, it is more desirable to use the brush-like abrasive cloth described above, which is soft in its application to the surface to be polished and can contain a large amount of borisshy liquid. In this case, the polishing solution is sufficiently supplied over the entire area of the surface to be polished, and the precipitated Cu is uniformly frictionally peeled off by the abrasive grains, so that there is no variation over the entire area of the surface to be polished, as shown in Figure 3. A substantially uniform polishing amount distribution of 101 μm or less can be obtained. The Si substrate to be processed used in this example had a convex surface of 100 to 200 mm on the side to be polished.
(μm) of 100 [mmφ] single crystal Si
The polishing speed obtained in this example was 15 μm for the substrate.
/ familiarity] level.

なお本発明のCuめっき・ボリノシー液に於ける化学反
応成分の組成は、上記実施例の組成に限られない0又混
入する砥粒はSiCに限らすA40s+5i02等でも
同様の効果を有する0 (f)  発明の詳細 な説明したように本発明によれば、そり等によ9曲面状
に形成されているシリコン基板面全域を、その表面に沿
って一様な深さに高速で、しかもダメージを与えずに研
摩することができるO従って本発明の方法をその製造工
程に適用することにより半導体IC等の製造歩留まシの
向上が図れる。
Note that the composition of the chemical reaction components in the Cu plating/volinosity solution of the present invention is not limited to the composition of the above embodiments, and the abrasive grains mixed in are limited to SiC. ) As described in detail, according to the present invention, the entire surface of a silicon substrate, which is formed into a nine-curved shape by warping or the like, can be coated at a uniform depth along the surface at high speed and without damage. Therefore, by applying the method of the present invention to the manufacturing process, it is possible to improve the manufacturing yield of semiconductor ICs and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(イ)及び(ロ)は従来の銅めっきポリ、シング
方法に於ける研摩量の面内分布図、第2図は本発明の一
実施例に用いた片面研摩装置の模式断面図で、第3図は
本発明の一実施例に於ける研摩量の面内分布図である。 図に於て、1は平板状回転テーブル2,2はボリノシー
・バンド、3は被処理基板固持板、4は支軸蓋ポリノシ
ー液注下管、5はサセプタ、6はシリコン被処理基板、
7はポリソシー液注入矢印し、8はポリソシー・パッド
の回転を示す矢印し、Sはシリコン基板、PRは合成皮
革様ボリッシー・パッド、PBはブラシ様ポリソシ=・
パッドを示す。 ← 1 因 (4) 一4a−3り−どθ−Aりθ/θ2ρJO#[nマー]
−蕩1才反・呼・、、・い、のブヒ鰺   −(ソー u3″″ z3θ] −基板甲11・らの距離一 番? 閃 トl/ ( 心 5閉 =基オ反17曳゛ ワ・ら・1巨詣井  −−→322
Figures 1 (a) and (b) are in-plane distribution diagrams of the polishing amount in the conventional copper plating polysing method, and Figure 2 is a schematic cross-sectional view of a single-sided polishing device used in an embodiment of the present invention. FIG. 3 is an in-plane distribution diagram of the amount of polishing in an embodiment of the present invention. In the figure, 1 is a flat rotary table 2, 2 is a volunty band, 3 is a substrate holding plate, 4 is a spindle cover polynosy liquid injection tube, 5 is a susceptor, 6 is a silicon substrate to be processed,
7 is a policy liquid injection arrow, 8 is an arrow indicating the rotation of the policy pad, S is a silicon substrate, PR is a synthetic leather-like policy pad, PB is a brush-like policy pad.
Showing pads. ← 1 Factor (4) 14a-3rd θ-Ari θ/θ2ρJO# [nmer]
- 1 year old anti-call...,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, anti-call, - (so u3'''', z3θ] - the distance between the board and A11, et al. is the best? flash l/ (heart 5 closed = group o's anti-17) Wa・ra・1 Komaidei −−→322

Claims (1)

【特許請求の範囲】[Claims] 回転するポリノシー・パッド上に硝酸銅とぶつ化アンモ
ニウムを主成分とし砥粒を含有せしめた銅めっきポ1ル
シュ液を注下しつつ、該ポリッシュ・パッド面と半導体
基板面を接触せしめることにより該半導体基板面の化学
研摩を行うことを特徴とする半導体基板の研摩方法。
While pouring a copper plating polishing solution containing abrasive grains and mainly consisting of copper nitrate and ammonium chloride onto a rotating polishing pad, the surface of the polishing pad is brought into contact with the semiconductor substrate surface. A method for polishing a semiconductor substrate, the method comprising chemically polishing the surface of the semiconductor substrate.
JP58061783A 1983-04-08 1983-04-08 Method of polishing semiconductor base board Pending JPS59187457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58061783A JPS59187457A (en) 1983-04-08 1983-04-08 Method of polishing semiconductor base board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58061783A JPS59187457A (en) 1983-04-08 1983-04-08 Method of polishing semiconductor base board

Publications (1)

Publication Number Publication Date
JPS59187457A true JPS59187457A (en) 1984-10-24

Family

ID=13181027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58061783A Pending JPS59187457A (en) 1983-04-08 1983-04-08 Method of polishing semiconductor base board

Country Status (1)

Country Link
JP (1) JPS59187457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553430B2 (en) * 2003-07-30 2009-06-30 Climax Engineered Materials, Llc Polishing slurries and methods for chemical mechanical polishing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553430B2 (en) * 2003-07-30 2009-06-30 Climax Engineered Materials, Llc Polishing slurries and methods for chemical mechanical polishing

Similar Documents

Publication Publication Date Title
JP3605927B2 (en) Method for reclaiming wafer or substrate material
KR100321271B1 (en) Dressing tools for abrasive cloth surfaces and manufacturing methods
DE69503408D1 (en) Device for chemical mechanical polishing with improved distribution of the polishing composition
JPH1158220A (en) Polishing device
TW200603945A (en) A method and apparatus for conditioning a polishing pad
TW471996B (en) Method and apparatus for conditioning grinding stones
JPS59187457A (en) Method of polishing semiconductor base board
JP4855571B2 (en) Polishing pad and method of polishing a workpiece using the polishing pad
JPS6234509B2 (en)
JPS59187456A (en) Method of polishing semiconductor base board
JPH1158232A (en) Dressing tool and manufacture thereof
JP2001334457A (en) Wrap plate and machining device using it
JP3281563B2 (en) Vitrified bond tool and manufacturing method thereof
JP4064391B2 (en) SiC substrate for polishing pad processing
US20030027504A1 (en) Chemical mechanical polish pad conditioning device
JP2003001558A (en) Lapping table
JP2000141204A (en) Dressing device, and polishing device and cmp device using the same
JP2003309094A (en) Dresser for processing cmp
JPH02294032A (en) Method and device for polishing wafer
JP2002127011A (en) Cmp conditioner
JPS63212465A (en) Polishing method
JP4057322B2 (en) Abrasive and polishing method
JPH0453669A (en) Polishing method
RU2137251C1 (en) Method for cutting semiconductor monocrystals into chips
JPS61141142A (en) Method for grinding semiconductor wafer