JPS59184907A - Programmable controller - Google Patents

Abstract

PURPOSE:To obtain a programmable controller which gives no deterioration to the using efficiency of a memory by using a power flow register and a stack register to advance the logical arithmetic processing for each bit and therefore eliminating the invalid use of the memory. CONSTITUTION:A power flow register and a stack register are used to advance the logical arithmetic processing for each bit. For instance, a user program is described in machine words of a microprocessor 1 and stored in a user program memory 2. This user program is executed by the processor 1 together with a system program of a system memory 3. Then an input signal source of various switches, etc. is connected to an input unit 4. At the same time, various output devices are connected to an output unit 5. A bit extracting circuit 7 extracts the designated one of eight bits of the input/output data of an I/O memory 6. This extracted bit is set to an MSB, and other seven bits are all set at 0 or 1 to obtain the data of eight bits.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a programmable controller, and in particular to a programmable controller in which a user program is written in general-purpose microprocessor language and is directly executed by a processor. [con1-] -1--: Concerning n.

(Invention fV Ming) Like Zhou'IJI, the current programmable controller [
1-La is to make the user program easier for one person to understand54
The user program is written in a special three commands (referred to as P Cg words); - An interpreter system in which the microprocessor executes the user program while decoding it; the user program is written in the microprocessor machine; The processor is divided into two types that directly execute the actual fT. Naturally, the latter direct execution method is overwhelmingly advantageous in terms of the processing speed of the ]-97 program, and the direct execution method is adopted in cases where high speed is sought.

Even the direct execution method uses a special microprocessor developed for programmable controllers (rather than a general-purpose microprocessor that is commercially available). 1] - As is well known, the main processing content of a microprocessor is 1-bit logical sieves.In contrast, general-purpose microprocessors are designed to process 1 word in parallel, such as 4 bits, 8 bits, or 16 bits. has been
The architecture is not suitable for processing 1-bit logical operations. - As is well known, in a logical operation type programmable controller, one-bit logical operation processing is performed using a power low register (hereinafter referred to as PF register) and a stack register that stacks data i of this PF register. Let's move on. If this is to be realized using a direct execution method, the problem is how the microprocessor handles the PF register and stack register for 1-bit logical operations.

In a conventional programmable controller using the direct execution method, the microprocessor's ``1'' l-mulator is assigned to the above PF register, and the required address is assigned to 11 bits in 1 word of the 8-bit numulator. The data is stored with the other 7 bits masked, making use of only 1 bit.
Bit logic operations are in progress. Furthermore, by using a stack operation instruction of the microprocessor, the data of the accumulator is stacked in an appropriate RAM area. In other words, whether it is a PF register or a stack register, (even though the valid data is 1 bit, l')
So, the 1-bit data and the masked 7-bit 1-
The data is combined into 1 byte, and all processing is performed in 1-byte units. As a result, memory usage efficiency becomes extremely poor.

4, due to the nature of the logical operation type instruction system, stacking and
It is sufficient if the number of stages of the register is about 8, and at the same time, in a normal knee program, the number of pushes in the stack is greater than the number of pulls, and the difference has no meaning at all. Therefore, in the interpreter type, when the stack register is bushed beyond the number of stages, the oldest data to be bushed is discarded in order. On the other hand, in the conventional direct execution method described above, processing is performed using the microprocessor's stack manipulation instructions, so it cannot deal with the meaningless phenomenon that the number of times the stack is pushed is greater than the number of times it is pulled. Although it is meaningless, it is necessary to reserve a memory area for the stack register according to the maximum allowable number of stack bushings, and in this respect, the memory usage efficiency is also significantly reduced.

(Objective of the Invention) The object of the invention is to realize a logic operation type program controller using a direct execution method using a general-purpose microprocessor without deteriorating memory usage efficiency. It is in.

(Structure and Effects of the Invention) In order to achieve the above object, the programmable controllers 1 to 1 of the logical operation type direct execution method according to the present invention have the following features:
Of the N bits of the accumulator of the microprocessor, the MSB or LSB is used as the power flow register, and the remaining N-1 bits are used as the stack register. Receives input/output data that is processed in parallel, extracts only one specified bit out of N bits, and converts that one bit into MSB or LS.
[Place M l/ in 3 and set all other N-1 bits to 110
The present invention is characterized in that a P1-extraction circuit is provided which outputs N-bit data offset by 1°'.

With this configuration, 1-bit logical operation processing can be performed elegantly.
It is possible to advance in units of 1 bit, eliminating unnecessary use of memory, and making it possible to configure an efficient controller.

(Description of Embodiments) FIG. 1 shows the hardware configuration of a programmable controller 1 to a roller according to the present invention. In this example (
A '380'9 series microprocessor 1 is used. The user program is written in machine language in the microprocessor 1 and stored in the user program memory 2, as will be described later.
is stored in The microprocessor 1 executes a user program in a user program memory 2 and a system program stored in a system memory 3. Input signal sources such as various switches related to equipment to be controlled are connected to the pano unit 4, and various output devices such as Iζ relays and solenoids are connected to the output unit 5.

The I10 memory 6 temporarily stores input data given to the input horn unit 4 from the outside, and also temporarily stores output data calculated by the microprocessor 1 and used to drive an external device via the output unit 5.

In the controller of the invention, the I10 memory 6 is coupled to the microprocessor 1 via a bit extraction circuit 7.

The pill extraction circuit 7 receives input/output data that is accessed by the microprocessor+#1 and is read and written in 8 bits (1 byte) in parallel to the ■/'0 memory 6 by a serial number.
Extract only one specified bit from among the bits, place that one bit in the MSB, and set all other 7 bits to “
101" or "1°゛! , = 8-bit data.

FIG. 2 shows one specific example of the bit extraction circuit 7; 16 bits I- output from microprocessor 1
Address signals ABO to ΔB15 (I), lower 11
Bits ABO to AB'10 are information specifying one bit of the 110 memory 6. ) Rano' dress information ABO
~AB7 is given to I10 memory 6, thereby I
One byte of data containing the specific one bit is output from the /O memory 6, and this one byte data is input to the multiplexer 7.1 of the bit extraction circuit 7. Also, the remaining information AB8 of the above address information. A
B9°Δ] 310 serves as a selection signal for the multiplexer (1), and as a result, the multiplexer 71 outputs only the 1-bit specified by - out of the 1-byte data read from the I10 register 6.

The 1-bit data output from the multiplexer 71 is output to the most significant bit (MSB) C7 of the data buses DO to D7 of the microprocessor 1 via the EOR gate 72 and the buffer gate 87. Address bus D O-D Remaining 7 bits Do-C of 7
6 is an address signal A input to gates 80 to 86.
By setting B13 to 0°', all outputs are "O" and "O". In this way, of the input/output data stored in bytes in the I10 memory 6, only one specific bit is output to MS[3 of the address buses DO to D7, and all other 7 bits are output to "0'' or 11'. Note that in order to invert the logic of the specific 1 bit and output it to the data bus D7, use the FOR gate 72.
It is sufficient if the address signal @AB12 inputted to the address signal @AB12 is set to 1.

Further, in the programmable controller of the present invention, the accumulator (A register>
10 is used as a PF register and a stack register for 1-bit logical operation processing. This situation is shown in Figure 3. Of the 8 bits of the accumulator 10, the MSB is used as the Pl-register, and the remaining 7 bits are used as the 7-stage stuff registers 1 to 1.
To read a specific 1 bit of the 0 memory 6 into the PF register, it passes through the bit extraction circuit 7 as in Ll, , -1 嘗ho.
The data signal DO-D7, in which a specific bit is placed in the MSB and all the remaining bits are O'', is logically summed with the contents of the accumulator 10, and the result is stored in the accumulator 10. ``11 Gotsu 41
I will do it with ORA life cold. In addition, to push the contents of the PIL register into stack registers 81 to S7 (1), use an instruction to the LSR of microprocessor 1,
You can move the accumulator 10 to the right. With this operation, PF→S1→32->S3→S4→S5→S6
→S7→C and Day now are jitted. On the other hand, to "remove the stack registers S1...S7 and move the latest data to the PF register", the LSLA instruction of the microprocessor 1 can be used to shift the 't7' 1:r-mulator 10 to the left. With this operation, C4-PF (-81←S2←S
Data is shifted as follows: 3←S4←S5←S6←S7←0.

In the programmable controller of the present invention configured as described above, for example, in order to perform sequence control expressed in the relay ladder diagram shown in FIG. The user program written in is stored in the memory 2.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the hardware configuration of a programmable controller according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the bit extraction circuit 7 in FIG. 1, and FIG.
The figure shows the state of use of the accumulator 10 of the microprocessor 1, and Fig. 4<8) shows a user program written in machine language to perform the control shown in the relay ladder diagram of the same figure (△). This is a diagram. 1... Microprocessor 2... User program memory 4... Input crab unit [5...... Output crab unit 6]
......I10 memory 7...
......Bit extraction circuit'10...
・・・・・・・・・Accumulator 1〕[：・・・・・・
...Power flow register 81 to S7...
Stack Register Patent Applicant Tateishi Electric Co., Ltd. Figure 1 Figure 2 Procedure Amendment (Method) 1. Indication of the case Patent application No. 5E158975 2, name of the invention Programmable controller 3, person making the amendment Relationship to the case Patent applicant address 10 Hanazono Tsuchido-cho, Ukyo-ku, Kyoto City Name
(294) Tateishi Kasuki Co., Ltd. Representative Takao Tateishi Contact information Tokyo Technical Relations Office Telephone 03 (436) 71
844, Agent 101 Address: 1-15-16-6, Uchikanda, Chiyo 01-ku, Tokyo, Column of agent of the application to be amended and Column 7 of the drawings of the description of the amendment. Contents (1) As per the attached amendment request (2) Details t11, page 11, line 14 [Diagram showing usage status, after 1, "Figure 4 (A> shows a control example)" Relay %i - Insert the description of Figure 1.

Claims (1)

[Claims] (1) A programmable microprocessor that directly executes a user program written in machine language using an N-bit parallel processing type general-purpose microprocessor, and uses power flow registers and stack registers to perform 1-bit logical pupil processing.
A controller which selects the MSB or L of the N hits of the accumulator of the microprocessor.
Let S'B be the above power flow register, and the remaining N'1
While reading the bits as the stack register, receiving the input/output data that is memory accessed by the microprocessor and processed in N bits in parallel, only one specified bit of the N bits is extracted. The present invention is characterized in that it is equipped with a bit extraction circuit that can output N-bit data by converting that one bit to MSB or LSB and setting all other If-1 bits to OI+ or "1". Programmable controller.