JPS59182582A - Gallium arsenide light emitting element - Google Patents

Gallium arsenide light emitting element

Info

Publication number
JPS59182582A
JPS59182582A JP58057038A JP5703883A JPS59182582A JP S59182582 A JPS59182582 A JP S59182582A JP 58057038 A JP58057038 A JP 58057038A JP 5703883 A JP5703883 A JP 5703883A JP S59182582 A JPS59182582 A JP S59182582A
Authority
JP
Japan
Prior art keywords
layer
gaas
single crystal
crystal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58057038A
Other languages
Japanese (ja)
Inventor
Kotaro Okamoto
岡本 孝太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Electronics Co Ltd
Original Assignee
Hosiden Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Electronics Co Ltd filed Critical Hosiden Electronics Co Ltd
Priority to JP58057038A priority Critical patent/JPS59182582A/en
Publication of JPS59182582A publication Critical patent/JPS59182582A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/0008Devices characterised by their operation having p-n or hi-lo junctions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To obtain the titled element excellent in crystallinity by forming a single crystal Ge layer on a single crystal Si substrate, a single crystal GaAs layer on the Ge layer, and a P-N junction in the GaAs layer. CONSTITUTION:When the N type single crystal Si substrate 11 is provided, the single crystal Ge layer 12 is formed on this substrate 11. For example, the N type single crystal GaAs layer 13 is grown on this layer 12 by e.g. vapor phase growing method of organic metal thermal decomposition. Then, the single crystal layer 14 of the conductivity reverse to that of said layer 13 is formed on this layer. Here, electrodes 16 and 17 are formed on the surface of the substrate 11 on the opposite side of the Ge layer 12 and on the GaAs layer 14, respectively. Since Ge and GaAs are equal in lattice constant, the excellent crystal of GaAs can be obtained.

Description

【発明の詳細な説明】 この発明はカリウム砒素のPN接合を利用して光を発生
させる(AAs発光素子に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AAs light emitting device that generates light using a potassium arsenide PN junction.

従来のGaAs発光素子は単結晶のカリウム砒素(以下
Qa Asと記す)基板上に、これよりも欠陥が少ない
良品T4の単結晶GaASを気相成長させて、この気相
成長層に’P N接合を形成していた。Ga As屯結
晶基板は高価であシ、特に大面積のものは得難い。一方
現在の半導体集積回路はシリコン基板 −上に’41成
したものが主流である。従ってシリコン基板に集積回路
を形成すると共に、これと機能的に関連したGa As
発光素子を形成できれば光−電気集積回路を構成するこ
とができ頗る便利である。
Conventional GaAs light-emitting devices are made by growing good T4 single-crystal GaAs, which has fewer defects, in the vapor phase on a single-crystal potassium arsenide (hereinafter referred to as QaAs) substrate, and forming 'P N in this vapor-phase grown layer. had formed a junction. GaAs crystal substrates are expensive, and it is particularly difficult to obtain large-area substrates. On the other hand, the mainstream of current semiconductor integrated circuits is those built on silicon substrates. Therefore, while forming an integrated circuit on a silicon substrate, a GaAs
If a light emitting element can be formed, an opto-electrical integrated circuit can be constructed, which is very convenient.

しかし単結晶Ga Asの格子定数は単結晶シリコンの
格子定数より4係程度大きいため、単結晶シリコン基板
上に単結晶Ga Asを直接形成することはできない。
However, since the lattice constant of single-crystal GaAs is about a factor of 4 larger than that of single-crystal silicon, single-crystal GaAs cannot be directly formed on a single-crystal silicon substrate.

この発明の目的は単結晶シリコン基板上に形成したQa
 As発人素子を提供することにある。
The purpose of this invention is to form Qa on a single crystal silicon substrate.
An object of the present invention is to provide an As starter element.

この発明1てよれば単結晶シリコン基板上VC中結晶ゲ
ルマニウム層が形成され、そのゲルマニウム層上に単結
晶Ga As層が形成され、その単結晶GaAs層にP
N接合が形成される。このようにゲルマニウム層を設け
ることにより単結晶シリコン基板と単結晶Ga As層
との格子整合が行われ、結晶性の良好な単結晶Qa A
s層が得られる。発光素子としてはQa As層の結晶
性が特に良好であることが好ましく、この点からゲルマ
ニウム層のj!−さは0.05μ〜0.1μ程度が好ま
しい。
According to this invention 1, a crystal germanium layer is formed in a VC on a single crystal silicon substrate, a single crystal GaAs layer is formed on the germanium layer, and a P layer is formed on the single crystal GaAs layer.
An N-junction is formed. By providing the germanium layer in this way, lattice matching between the single crystal silicon substrate and the single crystal GaAs layer is achieved, resulting in a single crystal QaA with good crystallinity.
An s-layer is obtained. As a light-emitting element, it is preferable that the QaAs layer has particularly good crystallinity, and from this point of view, the j! - The thickness is preferably about 0.05μ to 0.1μ.

以下この発明によるGa As発光素子の実施例を図面
を参照して説明する。図において例えばn形の単結晶シ
リコン基板11が設けられ、この基板11の厚さは例え
ば500μ程度であり、このシリコン基板11上に単結
晶ゲルマニウム層12が形成される。ゲルマニウム層1
2の厚さは0.05μ以上、好ましくは0.05μ〜0
1μとされる。
Embodiments of the GaAs light emitting device according to the present invention will be described below with reference to the drawings. In the figure, for example, an n-type single crystal silicon substrate 11 is provided, and the thickness of this substrate 11 is, for example, about 500 μm, and a single crystal germanium layer 12 is formed on this silicon substrate 11. germanium layer 1
The thickness of 2 is 0.05 μ or more, preferably 0.05 μ to 0
It is assumed to be 1μ.

0.05μJdTではシリコンとOa Asとの良好な
格子整合が困難であり、また余シ厚くしてもGa As
の結晶性が悪くなる。このゲルマニウム層12の形成は
シリコン基板11を400〜500°Cに加熱し、真空
度10−6TorrJJ、■で、成長速11flカ10
′A7秒り、■で電子ビーム蒸着法により行う、この成
長速度は遅い方が結晶成がよく、10A/秒以上に速く
するとゲルマニウム層12の表面に凹凸が生じて好まし
くない。ゲルマニウム層12の形成は熱加熱による蒸着
、いわゆる真空蒸着によってもヨく、あるいは先ず非晶
質(アモルファス)のゲルマニウム層を形成した後、熱
やレーザによシアニールして単結晶化してもよく、また
化学的気相成長法、(CVD)によって形成してもよい
At 0.05μJdT, it is difficult to achieve good lattice matching between silicon and OaAs, and even if the thickness is thicker, GaAs
crystallinity deteriorates. This germanium layer 12 is formed by heating the silicon substrate 11 to 400 to 500°C, at a vacuum level of 10-6 TorrJJ, and at a growth rate of 11 fl/10
The crystallization is carried out by electron beam evaporation at 7 seconds A and 2. The slower the growth rate, the better the crystal formation, and if it is faster than 10 A/second, the surface of the germanium layer 12 will become uneven, which is not preferable. The germanium layer 12 may be formed by vapor deposition by thermal heating, so-called vacuum vapor deposition, or by first forming an amorphous germanium layer and then cyannealing it by heat or laser to make it into a single crystal. Alternatively, it may be formed by chemical vapor deposition (CVD).

ゲルマニウム層12上に例えばn形の小結晶GaAs層
13が形盛される。Ga As層13の厚さは例えば6
0μ程度とされる。この形成は例えば有機金属熱分解気
相成長法(MOCVD法)、にょシ行われ、その成長条
件としてはガス流量モル比でAsH3(7#シン)/T
MG()リメチルカリウム)ヲ10〜100好ましくは
10〜24、Si H4(シラン) / T M Oを
O〜10×10−3好マLlj:2〜44X10 とし
、基板温度を4oo〜9oo0C好ましくは500〜6
5o0Cと、成長速度を0.001〜1μ/分とする。
For example, an n-type small crystal GaAs layer 13 is deposited on the germanium layer 12 . The thickness of the GaAs layer 13 is, for example, 6
It is assumed to be about 0μ. This formation is carried out, for example, by metal organic pyrolysis vapor deposition (MOCVD), and the growth conditions are AsH3 (7# thin)/T
MG (limethylpotassium) is 10 to 100, preferably 10 to 24, Si H4 (silane) / TMO is 0 to 10 x 10-3, preferably 2 to 44 x 10, and the substrate temperature is preferably 4 to 9 0C. is 500-6
5o0C and a growth rate of 0.001 to 1 μ/min.

結晶性の良好なものを得る点からは載板?温度をなるべ
く低くし、かつ成長速度を遅くすることが好ましい。ま
た前記ガス流計モル比とすることによりAsとGaとを
はN1:1で成長させることができ、良品質の結晶が得
られる。5iI−14はn形にするだめのものであり、
Asを多くすることによってもn形に近すけ、Asを少
なくすることによりp形に近ずけることができる。
Is it listed in terms of obtaining good crystallinity? It is preferable to keep the temperature as low as possible and slow the growth rate. Further, by setting the molar ratio of the gas flow meter as described above, As and Ga can be grown at a ratio of N1:1, and a high quality crystal can be obtained. 5iI-14 cannot be converted into n-type,
By increasing the amount of As, it can be made closer to n-type, and by decreasing the amount of As, it can be made closer to p-type.

n形にするためにはSe 、 S 、 Teなどを不純
物として用いてもよい。
In order to make it n-type, Se, S, Te, etc. may be used as impurities.

単結晶GaAs層13上にこれと逆導電形の単結晶Ga
 As層14が形成され、これら間にPN接合15が形
成される。この例ではp形の単結晶GaAs層14が形
成される。このGa As層14の厚さは例えば12μ
であり、Ga As層13の成長に連続して気相成長さ
せることができ、この場合p形不純物、例えばZnを含
むガスも同時に供給する。あるいはGa As層13上
にp形不純物の熱拡散やイオン注入などによってp形Q
a AS層14を形成することもできる。p形不純物と
してばSi、Geなどを用いることもできる。
On the single-crystal GaAs layer 13, a single-crystal Ga of the opposite conductivity type is formed.
An As layer 14 is formed, and a PN junction 15 is formed therebetween. In this example, a p-type single crystal GaAs layer 14 is formed. The thickness of this GaAs layer 14 is, for example, 12μ.
Therefore, vapor phase growth can be performed successively to the growth of the GaAs layer 13, and in this case, a gas containing a p-type impurity such as Zn is also supplied at the same time. Alternatively, p-type Q
a AS layer 14 can also be formed. Si, Ge, etc. can also be used as the p-type impurity.

シリコン基板11のゲルマニウム層12と居対1創の面
及びGa As層14上にそれぞれ電極16゜17が形
成される。
Electrodes 16 and 17 are formed on the surfaces of the germanium layer 12 and the GaAs layer 14 of the silicon substrate 11, respectively.

このようにして得られたGa As発光素子に対し、電
極1.6 ’、17間に順方向に電流を流すことによV
 =長897 nmの光の発生を確認した。なお基板の
みをシリコンの代りにGa Asとし、その他は同一条
件でGa As層13.14を形成した場合は波長87
31mであった。
By passing a current in the forward direction between the electrodes 1.6' and 17, V
The generation of light with a length of 897 nm was confirmed. In addition, when only the substrate is made of GaAs instead of silicon and the GaAs layers 13 and 14 are formed under the same conditions, the wavelength is 87.
It was 31m.

以上述べたようにこの発明によればゲルマニウム層12
を介在することによシリコン基板11上にGa As発
光素子を形成することができる。つま9シリコン基板1
1に対しゲルマニウムが混晶し、その上にゲルマニウム
の単結晶層12ができ、ゲルマニウムとGa Asとは
格子定数が等しいためにQa ASの良好な結晶が1昇
られる。シリコン基板はGaAs基板よりも安価であり
、しかも大面積のものも容易に人手でき、それだけQa
 AS発光素子を安価に作ることができる。まだシリコ
ン基板上に集(^回路を形成し、そのシリコン基板上に
GaAs発光素子を形成することによシ、新しい成能を
もつ光−電気集積回路を作ることができる。更にシリコ
ン基板は熱伝導率が良いため、放熱効果が高いものが得
られる。シリコン基板11をp形、GaAs1唾13を
p形、Ga As層14をn形とそれぞれしてもよい。
As described above, according to the present invention, the germanium layer 12
A GaAs light emitting element can be formed on the silicon substrate 11 by interposing the above. Toe 9 silicon substrate 1
1, germanium is a mixed crystal, and a single crystal layer 12 of germanium is formed thereon, and since germanium and GaAs have the same lattice constant, a good crystal of Qa AS is raised by 1. Silicon substrates are cheaper than GaAs substrates, and can be easily fabricated with large areas by hand, resulting in lower Qa.
AS light emitting elements can be manufactured at low cost. By forming integrated circuits on a silicon substrate and forming GaAs light emitting devices on the silicon substrate, it is possible to create opto-electrical integrated circuits with new capabilities. Since the conductivity is good, a product with high heat dissipation effect can be obtained.The silicon substrate 11 may be of p-type, the GaAs layer 13 may be of p-type, and the GaAs layer 14 may be of n-type.

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの発明によるGa As発光素子の一例を示す断
面図である。 11:単結晶シリコン基板、12:ゲルマニウム層、1
3 、14 : Ga As層、15:PN接合、16
.17:電極。 特許出願人  星電器製造株式会社
The figure is a sectional view showing an example of a GaAs light emitting device according to the present invention. 11: Single crystal silicon substrate, 12: Germanium layer, 1
3, 14: GaAs layer, 15: PN junction, 16
.. 17: Electrode. Patent applicant: Hoshi Denki Manufacturing Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] (1)  単結晶シリコン基板と、そのシリコン基板上
に形成された単結晶ゲルマニウム層と、そのゲルマニウ
ム層上に形成された一導電形の単結晶第1カリウム砒素
層と、その第1カリウム砒素層上に形成され、これとP
N接合を形成している逆導電形の単結晶第2カリウム砒
素層とよシなるOa As発光素子。
(1) A single-crystal silicon substrate, a single-crystal germanium layer formed on the silicon substrate, a single-crystal first potassium arsenide layer of one conductivity type formed on the germanium layer, and the first potassium arsenide layer. formed above, and this and P
An OaAs light emitting device with a single crystal second potassium arsenide layer of opposite conductivity type forming an N junction.
JP58057038A 1983-04-01 1983-04-01 Gallium arsenide light emitting element Pending JPS59182582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58057038A JPS59182582A (en) 1983-04-01 1983-04-01 Gallium arsenide light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58057038A JPS59182582A (en) 1983-04-01 1983-04-01 Gallium arsenide light emitting element

Publications (1)

Publication Number Publication Date
JPS59182582A true JPS59182582A (en) 1984-10-17

Family

ID=13044267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58057038A Pending JPS59182582A (en) 1983-04-01 1983-04-01 Gallium arsenide light emitting element

Country Status (1)

Country Link
JP (1) JPS59182582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068695A (en) * 1988-04-29 1991-11-26 Sri International Low dislocation density semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016487A (en) * 1973-04-30 1975-02-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016487A (en) * 1973-04-30 1975-02-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068695A (en) * 1988-04-29 1991-11-26 Sri International Low dislocation density semiconductor device

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