JPS59181841A - Error correcting and decoding system - Google Patents

Abstract

PURPOSE:To perform correction and decoding until a prescribed threshold value is obtained by adding a subtraction circuit to a majority decision circuit so as to set a threshold value to be decided of the majority decision circuit to a specific value within the number of the input devices of the majority decision circuit and subtracting this threshold value to be decided via the subtraction circuit after cyclic correction. CONSTITUTION:A CPU sets a threshold value designating signal 129 to ''17''. Then, the CPU generates a start signal 110 to reset 124 a syndrome register 106. Further, the CPU loads sequentially 1-packet 272-bit information by 16-bit each in 17 divisions. the loaded data is superimposed on a data 114 before error correction to generate a load instruction 111. A load gate signal 120 is generated based on this signal 111 to attain data loading before error correction and 16-bit shift to registers 103 and 106. When this procedure is repeated 17 times, the generated syndrome is stored in the register 106. Then, the correcting operation is commanded by the CPU. After the error correction of 16-bit is performed by a correcting signal 113, the CPU reads a data 115.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for correcting errors in character code horn Q transmission by ingesting and transmitting digitally coded character information during the vertical retrace period of a TV broadcast and displaying it on a home television receiver. −
It is related to the decoding power formula, and has significantly improved error correction ability compared to the conventional decoding power formula. The present invention relates to a t-correction decoding circuit.

Conventionally, it has been considered best to use the (272, 190) code as the error correction method for single character code broadcasting. This means that the applicant's patent application II/15
This is also clear from No. 8-13579 "Error Correction Decoding System".

1-Using the basic error correction 11 three-system decoding circuit proposed in Japanese Patent Application No. 58-6579 mentioned above, one no.
It was found that it is possible to correct errors of 8 bits in bits (272 hints), but errors of 9 bits or more cannot be corrected at all.

In addition, another improved error correction decoding method proposed in "Double Output" (i.e., when an error cannot be corrected, it is possible to correct errors of 9 or more hits by shifting the leading bit). However, the disadvantage of using this method was that the processing time was too long.

In view of the above-mentioned points, it is an object of the present invention to provide an error correction decoding system that improves error correction capability and reduces processing time at the same time.

In order to achieve such an object, the present invention adds a subtraction circuit to the majority decision circuit in an error correction decoding system including a majority decision circuit, a syndrome register, and a data register using a majority decision set cyclic code, and also adds a subtraction circuit to the majority decision circuit. The determination threshold of is set to a specific value within the number of input elements of the majority circuit, and after cyclic correction, g is calculated by a specific number sequentially from the determination threshold via a subtraction circuit, and the determination threshold is decreased until it reaches a predetermined value and corrected. The feature is that it can be decoded.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an error correction decoding circuit to which the present invention is applied. In this figure, 100 is an output port, lot
is a human power port, 102 is a parallel/serial-to-parallel conversion circuit, 103 is a data register (272 stages), and 104 is a timing-7
Enerator, +05 is the rotor gate 106 is the syndrome register (82 stages), 107 is the multi-decision circuit, 108
is the correct I/Kate circuit, +09 is the error status register, 110 is the start 4M number, and Ill is the low I/4
No. 8, 113 is a collect signal, 114 is data before error correction, 115 is data after error correction, +18 is serial load data, 117 is ready (+r '''T, 118
is a syndrome register signal, and 119 is an error. i+stop i'l Tsukasa, 120 is Roto Gate I8, 121 is Koretsu I・Ge 1-4R4, 122 is Roto timing signal, 123 is Ronk signal for Roto, 124 is Clear Eye, 126 is error correction Cronk. signal, 127 is an error status signal, 128 is a modulo-2 adder, 1
29 indicates a threshold designation signal (5 hits).

The basic circuit configuration of this embodiment is as described in the patent application filed in 1983-
Is it as stated in No. 6579?■ It is configured so that the interval can be changed depending on the threshold specification book 29, and ■The constituent elements of the majority vote are 1 bit, the first bit after shortening. The structure is different. By making them orthogonal on the first bit of the transmitted data, the load end signal is no longer necessary.

Next, the operation of this embodiment will be explained. The feature of this embodiment is that the threshold values are set to 17, 18, 15, 14, 13.
, 12, +1.10.8, the error correction ability is improved.

This principle will be described later.

First, the CPU (not shown) specifies the threshold level (threshold specification signal 129) as 17 (5-bit information). Next, C
The PU issues a start command (start signal 110) and sets all 82 pins +- tSa of the syndrome register 10G to “°0゛° (see t'yk signal 124).This causes the next load data to be set. Prepare.CP
U sequentially loads 1 packet of 272 bits of information into 17 times of 16 hits each. The CPU places the load data on the data 114 before the one-bit correction and generates a load command (see load signal 111).

Based on this Law) I, Ji 111, Law I Gutoi 1. '・-” 120 and low 1・clock message!
;(+6 bi.

j・) 123 tR=Ushishi, Syndrome Register 1
06 Hetator's Rotocate i. tll, a take load of the pre-error correction take 114 to the parallel-to-serial conversion circuit 102, a 16-bit I shift from the parallel-to-serial conversion circuit to the data register 103, and a 16-bit shift register 10G.

By repeating this operation 17 times, the first take reaches the leading edge of the data register 103. The syndrome register 106 has finished generating the syndrome. In other words, syndrome register 1 of 82by I□
06 represents the remainder when the take is divided by the generator polynomial G(2).

Here, S(x) is the syndrome, a.・・・・・・a
l, 11 bits of 272-bit data, g(x) is the generator polynomial described in Patent Application 1985-8579 t'3, (
) represents the remainder.

The error correction operation will now be explained. The CPU generates a collect signal 113 in response to the collect command. On the other hand, the timing generator 104t generates an error correction clock signal 126 for the data register 1.
Only 16 hints of data in 03 are error corrected and loaded into the serial-parallel conversion circuit 102. This error correction is performed by an exclusive OR circuit (modulo 2 adder) 108. Error Correction No. 14 1191, the states of the 82 syndrome registers are a linear combination of 1791 described later, and the majority vote among the 17] 1v each 107 to the threshold (the first dark value is 17: threshold )-No. 129) is output.

However, this error correction signal 119 is configured to pass only when an error correction operation is performed in response to the collect signal.
(See 0B). Furthermore, the error correction signal 113C has an error j1
As in the case of the input operation, if there is an error in the hint, the syndrome register 106 is modified to remove the influence of that bit.

In this way, collect signal. No.113, Ke16bi.

I・の+;! 't. After performing 't111-, CP
II confirms that the ready signal +17 is active and reads take 115 of the human-powered boat lol. and,
Output collect signal 113 17 times, 1 pa, I 27
Restore 2 bits of belief. At this time, by checking the error stake No. 718 + 27, it is possible to judge whether the error correction has been made in the IF or not. Also, when the syndrome register lO6 is not all 0°',
Finally, since there is an error in one of the focus positions, the error correction operation is performed again. However, at this time,
Decrease across the threshold of the majority circuit. In other words, the darkness value is 1
6, the data after error correction 11 was performed in the previous Oka-i 1c-th 7 is used.

The following operations are performed until the threshold value 9 is completed. Tatashi,
When all the registers 106 become '0' in the middle, it means that the error correction operation has been completed.In other words, the data at that point is 11?
, there is no need to pass through the error correction circuit 11 after that. In addition, in the tree example, the input/output port is
- data is treated as 16 hints, but the same applies to other bit numbers.

FIG. 2 is a flowchart 1 showing the control procedure of FIG. 1. Here, in order to simplify the circuit, a composite check matrix is used that is not orthogonal at the shortened bits, but is orthogonal at the first bit of the actual transmission bits. As a result, the above-mentioned patent application No. 58-f
As disclosed in No. i578, it is no longer necessary to empty the syndrome register by the load end command signal. In other words, there is no need for a low end signal.

The contents of the syndrome register 10B are set to So.

Sl,...Sto,S,1, the composite change matrix A, , A that is orthogonal at the transmission head focus '2
, , ..., AIl is as follows.

A0=S.

AI =S++a ``Su A2 =34''sn A, =Ska +S,, +5au A6 =5. +S14 “Sll”5at
A1, ・chi. +55, +5. , +S,.

AI, “S7” S H)” Si.+S,.

A,,=S,,+Sl〒÷S4. +S47→S,.

All -8l +Sr. +S. t ””, 3 +5
17A! l=! %! l +S314S*z +b
ag "Ssq8. -S,, +S,, +SS
ll +Sg, +Sv* +5qyA, 12 ways, +
SJ6 +Sλ7 +S◆2 +St2'+St.

Al2-6 “SJ7+Sji+SJO+Sj3”Sa
A1β=sO “Su +5III” Sll + S
A, + S7 “5laA+i =S8”SLY
+Su “Ssr”Sit “StR”Sy+Aly
=S3 "Sl! +Syx +SB "".+S
KI÷S? .

A*-5I7"Sll+Sin+Sri"S'+2"S
l"S?2"S) Next, set the threshold of the majority circuit to 17. l
1li, 15. ..., I'll explain the benefits of going one after the other, starting with the highest rank. Now, as an example, let's try to predict the case of 17. In this case, the error is 1.
When the number is 6 or less, there is no possibility of making an incorrect 1-1-1 (incorrect corrections may be made in I-shiba-1-i-1-sei-9).

1 (composite Naenkuma when 1-subtracted vinyl 1, 1. is omitted)
・Rikusu is on a monthly basis like in 7 meals.

\ Destination: 1.1 of 16 or more at t- location excluding rf + hint
“There is only 1, 114, 1,1.” (The number of °゛1゛° in 41'1 of Lipakun and Matrix A is
111/Dog is also 16'", +4"J (1 white is 1
7 does not include 11"l revision 11. In other words, +
I': L Tsuda revision 11- is not '41. In addition, if 16 or more dots occur in a location that includes the first hint, JJ between 1.1 Llt repattern and matrix A is performed.
The number of "l" in "ll" may be 17. Naturally, if there are only 1 and 1 at the beginning, the number will be 17. Even if there are 15 errors, the number of "l" will be 17 if the first hi and l are placed only in each line of the previous A. In such a case, the first hit will be stopped at 111, and error correction will be performed only for the first focus. Since the above-mentioned operation is repeated 272 times, by setting the number 111 to 17, some of the problems with itj% of 16 or more cards will be corrected. Moreover,
There will be no incorrect revision IF.

Finally, if you raise tri to 16 and perform the same operation as described in 1->ll+, there will be no incorrect corrections for more than 15 errors, but some correct error corrections will be made. Become, become two.

In addition, 1 toma 1 i direct 15.14.13.12, 11.
Set to to and perform 1.1'' iE. This will correct a considerable error of 16 hits to 8 bits.

Finally, the original threshold value 8 is set to perform error correction. In this case, all remaining errors of 8 pinto or less can be corrected by the inherent code error correction ability.

- As mentioned above, by lowering the threshold to 17 to 8 and sequentially performing error correction, it is possible to correct all errors of 8 pints or less and most of the 1 errors of 9 bits to 16 bits. .

FIG. 3 shows a second embodiment to which the present invention is applied. Fourth
The figure is a flowchart showing the control procedure of the CPU (not shown).

The error correction circuit shown in FIG. 1 is of a type in which the IAI value is reset each time, data obtained by the previous error correction is loaded again, and correction is performed accordingly. for that,
This will require considerable processing time. 31')/,
1, ``<shita 13' (revised jF-circuit, person 1゛i [
The circuit configuration is essentially the same as that shown in Figure 1, or the so-called revision II-processing and 12j (tr+ settings are automatically performed). The difference is that the structure is different.The components that have almost the same functions as the components shown in Figure 1 are different from each other.

In this figure, 300 is a data selector, 301 is a timing generator, 302 is a majority circuit, 303 is a data read signal, 304 is a dummy clock signal, 305
is the data load clock signal, 306 is the collect clock signal, 307 is the storage data to be used next time, 3
08 represents the serial data after the error correction 11, and 308 represents the timing signal at the time when the test for one packet of takes is completed.

As mentioned in FIG. 1, the CPU <not disclosed) generates a start card q110. This start 4'V
In response to ":', the timing generator 301 generates the reset, 1 signal 124, clears all registers in the syndrome register +06, and sets 1J51 (+fj to 17) of the majority circuit 302. The CPU selects a parallel take I-L as a take 114 before error fixing, generates a rotat signal Ill, and loads the data.Loading to the parallel-to-serial conversion circuit 102 is performed using the load clock signal +22. After the low F, data is loaded into the data register 103 and the syndrome register IO'6 in response to the load clock signal 123.The data selector 300 passes the low data during loading and the storage data 307 during error correction. This gate circuit is used to complete the data row (.) of all 272 bits of data.

When the take load is completed, timing generator 3
01 outputs a signal for error correction operation.

That is, the correct game I circuit 108 is opened, and the correct game I circuit 108 is incremented by the syndrome register 106, the data register 1.03, and the data register 1.03. ] Error correction. The threshold value used initially is 17. This error correction operation is similar to that described in FIG.
272 hin)・About dividing. This 11j
7. Z-1:,j! in take register 103. ζ1 confession is processed as 17, and 1. at t2. tree + ql' i
Take 272 after t 1 hin left.

At this stage, if the error status (rT No. 127) indicates an error, it means that there is still an error in the data in the take register 103. Therefore, in this case, 1!ζl Subtract by 1 and perform 111 error correction + F.

When the multi-order decision circuit 302 receives the error status 127 and determines that there is still an error, it responds to the timing of the packet end signal and sends the signal 1j41 (
+ Express white by 1 to 11. Syndrome register 106 has a period of 273 cycles, so by Tammy Cronk (,i L3304, syndrome register 1
06 by 1 hin;・shift)・. After that, use threshold A1/gate 8 to +flt [T +E].

All errors are corrected and error status I4+H2
7, the CPU starts reading data.

Also, even if Oka 4 + R4 was 9, Sawa corrected the error by 11- and there was no 0, and Sawa said that Error Stake No. 7111 127
ni,,+□1represent J\? As well as being a lady (,S
+II7 is output.

Tei - Evening 1; N seepage is data toy iris number 303
done in response to. Directly change the data in the take register 103 using the data storage system Cronk 305]! Lead to circuit +02. In response to the ready signal 117, C
The PU repeatedly outputs the data read signal 303 for reading the parallel take 115, resulting in an error; +r
Restore data for 1 Pakento after 1+2.

FIG. 5 is a block diagram illustrating the operation of the majority circuit. Here, 500 is the majority input signal (A.

~A), 501 is a majority circuit, 502 is a subtraction circuit, 5.031-1L gate circuit, 504 is a subtraction command signal to reduce the threshold by 1, 505 is a threshold signal, 50
6 is a majority vote output signal. In addition, as mentioned above, 108
1 is a collect gate circuit, 124 is a clear signal, 127 is an error status signal, and 309 is a 1-paquent end signal.

7th line 3'J l''J road 502 is reset Iha No. 124
It is preset to ``17'' by . That is,
17 is the first sword 1 (becomes Nao. 1 tame 1 272
When each hint has been corrected for the bit, the 1-paquent work signal 309 instructs the gate I 503 to pass the error status signal 127, thereby sending out the decrement q command signal 504. This decrease command signal 50
4, the initially set threshold 17 is reduced by 1, and 1
6, it is determined and a threshold signal 505 is sent out. The majority decision circuit 501 outputs the majority decision output signal 506 only when the majority decision input (M numbers A0 to A) is greater than the threshold specified by the threshold signal 505. This is performed for each bit, and the operation at the threshold 16 is completed. .

Furthermore, the above-mentioned operation is repeated for each field value of 15 to 8.

In each of the embodiments shown in FIGS. 1 and 3, the threshold value is set to 17. . . , 8, but the processing time can be shortened by setting intermediate thresholds such as 11.10.8, for example.

In this case, the error correction ability will be slightly lower than in the embodiment described above. That is, in this case, Riko will correct all errors in 8 bins) and below, and the number of errors in 8 hits and 10 bits. Also,
14 (By setting Kf to, for example, 17.15.+3.II,9, the error correction operation can be similarly completed in a short time.

- As explained, according to the present invention, 1 packet I.
All errors of 8 pints or less can be corrected, and errors of 9 bits or 16 bits or less can be corrected at a considerable rate, so it is possible to expand the service area of character code broadcasting and reduce error display. I can do it. According to computer simulations, it was possible to correct errors at 100% for 9 bits) and 10 bits, and about 95% for II hits.

Note that in the first embodiment shown in FIG. 1, only the threshold value can be specified from the outside without changing the basic error correction circuit, so the software, q[( By adding 1) (1), there is an advantage that it can be realized in 1.

In addition, the second -U embodiment, which is smaller than that shown in FIG.
f - the first embodiment of the first embodiment
- Since it is realized by hardware, high-speed processing is possible.

In the third embodiment described later, the number of types of cleavage thresholds that are lowered by the mnth order is reduced, so that the 1st revision i1E
The time required for this can be reduced.

As described above, the present invention can be applied to character code I/broadcasting that utilizes the vertical retrace period of television broadcasting, but the present invention is applicable to 1. broadcasting that uses the entire television blanking line. Of course, it can also be applied to code broadcasting of Ij waveforms. Furthermore, it can also be applied to other majority decision 'jq code decoding circuits.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing one embodiment of the present invention, FIG. 2 is a flowchart 1, which shows the control procedure of FIG. 1, and FIG. 3'th
FIG. 5 is an explanatory diagram of the operation of the majority circuit. 100...Output is -1-. 101... Human power port, 102... Direct/parallel conversion circuit, 103... Data register, +04... Timing generator (/-ri, 105...
Load key (・Circuit, +06...Syndrome Resistance, 107...Majority circuit, 108...Collect gate circuit, 109...Error status register, 110...
Start signal, ill...Rot believe, 113...Collect signal, 114...Data before error correction, 115...Data after error correction, 116...Serial rot data, 11? ...Ready signal, 118...Syndrome register signal No. 5, 118...
・, 1 tree 1, 1 Ichihakuyumi, 120... Roto Katei, ゛, X″f, 121
・・Collect K-1・VJ, +22・Rot timing (t”+ 'i, +23・Long signal for load?, 124・Recent key C) 53. 12B・・1(ri) Revised 11 Kron Kui F) ke, 127
...Error status server number, 128...Adder modulo 2, 128...Fj designation signal, 300...Data selector, 301...Timing generator, 302...Majority circuit , 303...Cheetary Toy Shouji, 304...Tammy Clock Isoji, 305...Decrete Clock Signal, 306...
Collect clock old issue, 307... Data for storage, 308... Serial data after error correction, 309...
Bow packet entent signal No. 1, 500...majority decision power value °・), 501...majority decision circuit, 502...j a circuit, 503...gate circuit, 504...-1 command signal, 505...1 tree rj ihe issue, 506...
Majority output signal. Patent Applicant 1 "Thursday Broadcasting Corporation Figure 4 Figure 5 Figure 1 Ha6ke/Fei 4ro No.

Claims (1)

[Scope of Claims] l) In an error correction decoding system including a majority decision circuit, a syndrome register, and a data register using a Tasa decision difference set cyclic code, 41 subtraction circuits are added to the majority decision circuit, and the majority decision circuit is The judgment threshold of the circuit is set to a specific value within the number of majority circuit input elements, and after cyclic correction, i
i: An error correction decoding system characterized in that a specific number is sequentially subtracted from a determination threshold through an S subtraction circuit, and correction decoding is performed by increasing the sensitivity until the determination threshold reaches a predetermined value. 2) Data signal 272 bits, information signal 190 bits
Using a signal of 82 bits and parity bit I,
Setting the determination threshold of the majority decision circuit to 17 in advance, and setting the specific number to 1, the determination IAI (+f
i l? The error correction decoding method according to claim 1, characterized in that the correction decoding is carried out by sequentially decreasing j by half (ifj until it reaches 9). 2. The error correction decoding system according to claim 1, wherein the error correction decoding system is changed based on a command from a computer. 4) Error correction decoding according to claim 1, wherein the determination threshold setting and data reloading operations are performed by hardware to shorten error processing time and reduce the burden on software. method. 5) The error correction decoding power formula according to claim 1, wherein the amount of decrease of the determination threshold value is set to 2 or 3 to shorten the error correction time. 6) The error correction decoding system according to claim 1, characterized in that the determination amount A1 is started from 13 to shorten the error correction time.