JPS59181571A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59181571A
JPS59181571A JP5360083A JP5360083A JPS59181571A JP S59181571 A JPS59181571 A JP S59181571A JP 5360083 A JP5360083 A JP 5360083A JP 5360083 A JP5360083 A JP 5360083A JP S59181571 A JPS59181571 A JP S59181571A
Authority
JP
Japan
Prior art keywords
region
contact
electrode
aluminum
boron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5360083A
Other languages
Japanese (ja)
Inventor
Toru Takeuchi
竹内 透
Katsuhiro Fujino
藤野 勝裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5360083A priority Critical patent/JPS59181571A/en
Publication of JPS59181571A publication Critical patent/JPS59181571A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Abstract

PURPOSE:To obtain the semiconductor device of electrode structure having an ohmic contact by a method wherein a high density impurity region is formed on the interfacial region of the semiconductor base layer which comes in contact with an electrode. CONSTITUTION:A contact compensation region 43 is formed on the electrode forming region located on the surface of a p type region 42 by selectively and shallowly introducing high density of boron into an n type silicon substrate 41. An insulating film 44, a titanium nitride layer 45, and an aluminum/silicon layer 46 are coated, and a wiring and an electrode having aluminum as the principal ingredient are formed by performing a patterning. When the boron density of the contact compensation boron containing region 43 is low, a voltage-current line has a non-linear form, which is non-ohmic contact in other words, but as the boron density becomes higher, said line is turned into a linear form, thereby enabling to obtain an ohmic contact.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は牛努体装置、特にその電・直構造に関ターる。[Detailed description of the invention] (1) Technical field of the invention TECHNICAL FIELD The present invention relates to an electric power system, particularly to its electrical and direct structure.

(2)従来技術と問題点 半導体装置の電極材料としてはアルミニウムが一般的に
用いられている。第1図は通常の電極窓の例である。n
形シリコン基板11にp影領域12を形成し、絶縁ノ曽
13で覆ってから電極窓開けし、アルミニウムで電極1
4を形成する。ウエリー処理の偵々の工程の熱処理にお
いてアルミニウムはシリコンを吸い上けるので、アルミ
ニウム(金属)とシリコン(半導体)の境界面15が変
形し、拡散層の突抜けが起る。父、例えば、第2図にお
けるn形シリコン基板21内のp影領域22のように薄
い層状領域とアルミニウム電極23が接していると、ア
ルミニウムがシリコンを吸い上げる結果、p影領域22
を通シ越し2てその下層たるn影領域21とアルミニウ
ム電極23とが短絡する事態も発生しやすい。
(2) Prior Art and Problems Aluminum is generally used as an electrode material for semiconductor devices. FIG. 1 is an example of a normal electrode window. n
After forming a P shadow region 12 on a shaped silicon substrate 11 and covering it with an insulating layer 13, an electrode window is opened, and an electrode 1 is formed using aluminum.
form 4. Since aluminum sucks up silicon during the heat treatment of the Welly process, the interface 15 between aluminum (metal) and silicon (semiconductor) is deformed, causing penetration of the diffusion layer. For example, when the aluminum electrode 23 is in contact with a thin layered region like the p shadow region 22 in the n-type silicon substrate 21 in FIG.
A short-circuit between the n-shaded region 21 and the aluminum electrode 23, which is the lower layer of the through-hole 2, is likely to occur.

こうした事態を回避するために、従来、アルミニウム電
極にシリコンの吸い上げを阻止するバリヤが設けられて
いる。第3図を参照すると、3]はn形シリコン基板、
32はp影領域、33は絶縁膜である。アルミニウム電
極は3層構造をなし、下側から、シリコンとのオーミッ
クコンタクトを形成するための厚さ100OX程度のア
ルミニウム1134、シリコンのアルミニウム内への上
昇を阻止する厚さ150OX程度の例えばTIN。
To avoid this situation, aluminum electrodes have conventionally been provided with a barrier to prevent silicon from being sucked up. Referring to FIG. 3, 3] is an n-type silicon substrate,
32 is a p shadow region, and 33 is an insulating film. The aluminum electrode has a three-layer structure, starting from the bottom: aluminum 1134 with a thickness of about 100 OX to form an ohmic contact with silicon, and TIN, for example, with a thickness of about 150 OX to prevent silicon from rising into the aluminum.

ZrN + HfN * TaNなどのバリヤ層35、
そしてIpt極および配線本体をなす厚さ1μn1程度
のアルミニラム層36である。すなわち、TiNのよう
な閤融点金属の窒化物かアルミニウムのシリコン吸い上
げを阻止するバリヤとして用いられる。しかし、高融点
金属の窒化物はシリコンとの石、気的コンタクトかオー
ミックでないので、シリコンとの直接のコンタクF・に
はアルミニウム薄層が用いらf’している・このrl;
を極・構造は必ずしも牟純ではない。
A barrier layer 35 such as ZrN + HfN * TaN,
Then, there is an aluminum layer 36 having a thickness of about 1 μn1, which forms the Ipt pole and the wiring body. That is, a nitride of a metal with a melting point such as TiN or aluminum is used as a barrier to prevent silicon from being absorbed. However, since the high melting point metal nitride has no ohmic contact with silicon, a thin layer of aluminum is used for direct contact with silicon.
The polar structure is not necessarily pure.

以上はアルミニウムのシリコン吸い上ケ’を例とじ一〇
述べ/(か金とヒ化ガリウムとの相互、融合なども同じ
問題を孕んでいる。その点、高融点金属の窒化物e」、
at′*体の吸い上げあるいは半導体との融合という問
題がなく、かつ1lIi−j熱性に俊九ているので、′
電極材料として魅力的である。しかし、半導体との短気
コンタクトがオーミックでないのか問題である。
The above is an example of silicon siphoning from aluminum. (Also, the mutual or fusion of gold and gallium arsenide has the same problem.In that respect, nitrides of high melting point metals.)
At'
It is attractive as an electrode material. However, the question is whether the contact with the semiconductor is not ohmic.

(3)発明の目的 本発明は、以上の如き従来技術の現状に鑑み、筋融廣金
扶の窒化物を半導体と直接接触させかつオーミックなコ
ンタクトを持つ電極構造にした半導体装16をjH供す
ることを目的とする。
(3) Purpose of the Invention In view of the current state of the prior art as described above, the present invention provides a semiconductor device 16 that has an electrode structure in which a hard nitride is brought into direct contact with a semiconductor and has an ohmic contact. The purpose is to

(4)発明の溝成 そして、本発明は、半m体基増と接触する高融点金属の
窒化物からなる′上物を南する半榔体装直において、心
気的コンタクト惰イノ(のために電極と接する半導体基
層の界ホ4」領域にi湧娘度の不純物領域を形成するこ
とによって、上記目的を達成する。
(4) Formation of the groove of the invention The present invention also provides for the formation of an air-contact inertia in the refitting of a semi-molar body made of a nitride of a high-melting point metal that is in contact with a semi-molar base. The above object is achieved by forming an impurity region of i concentration in the boundary region of the semiconductor base layer in contact with the electrode.

尚、コこに冒1融点金植とはチタン、タンタル。Incidentally, the melting point metals used here are titanium and tantalum.

タンクステン、ハフニウム、モリブデン、ノルコニウム
、ニオブ、パナノウム、クロム等をいう。
This refers to tanksten, hafnium, molybdenum, norconium, niobium, pananium, chromium, etc.

以下、′犬廁り1」を用いてh発明する。Hereinafter, the invention will be made using 'Inuwari 1'.

(5)発明の実施例 第4凶を参照して説ψjする。n形ンリコン基板(比抵
抗ρ=2〔Ω・cm ) ) 41にホウ素を選択的に
導入してp形頭域(ρ、=800[Ω/口〕、深さCJ
im ]、ρ=20〔Ω/口〕)に選択的に導入しで(
拡散させる)コンタクト補償領域43を形成する(第4
図(イ))。絶縁膜44(例えは酸化シリコン膜、蟹化
ンリコン膜:厚さ1μm程度)を被着し、′1≦極窓を
囲ける(第4図(ロ))。
(5) Embodiment of the Invention The following will be explained with reference to the fourth example. N-type silicon substrate (specific resistance ρ = 2 [Ω/cm)] By selectively introducing boron into 41, p-type head area (ρ, = 800 [Ω/mouth], depth CJ
im ], ρ = 20 [Ω/mouth]).
forming a contact compensation region 43 (diffusion);
Figure (a)). An insulating film 44 (for example, a silicon oxide film, a silicon oxide film, about 1 μm in thickness) is deposited to surround the pole window where '1≦'1 (FIG. 4 (b)).

次いで窒化チタン層45を被層する(第4図(ハ))0
この窒化チタン層だけで電極を形成してもよいが、例え
ば1屋化チタン層45を厚さ1500X程度とし、その
上からアルミニウム/シリコン層46を被着し、パター
ニングすることKよって、アルミニウムを主体とする配
線および電極とし、そのシリコン吸い上げを窒化チタン
膜で1s14止する構造にすることかできる(第4図に
))。
Next, a titanium nitride layer 45 is coated (FIG. 4(c)).
Although an electrode may be formed using only this titanium nitride layer, for example, the single-layer titanium layer 45 is made to have a thickness of about 1500X, and the aluminum/silicon layer 46 is deposited on top of it and patterned. It is also possible to adopt a structure in which the main components are wiring and electrodes, and the suction of silicon is stopped by a titanium nitride film (see FIG. 4).

以上のようにして作成した電極のシリコンとの電気的コ
ンタクトを調べるために、同じn影領域42に電極を2
つ(第5図の51.52)形成し、73g5図に示す如
くこれらの間に電圧をかけてylH2’Lる電流ケ調べ
た。その結果を第6図に示すが、こt’tはコンタクト
補償ホウ素含有領域43のホウ素溪度を変えて、その抵
抗値ごとにグラフ化したものである。図から明らかなよ
うに、低抵抗値即ち示つ素濃度が低い場合には電圧−電
流線は非直線的即ち非オーミツクであるが、高抵抗値即
ぢホウ累濃度が畠くなるにつれて線が直線化し、オーミ
ックになっているのかインかる。
In order to examine the electrical contact between the electrodes created as described above and the silicon, two electrodes were placed in the same n-shaded area 42.
A voltage was applied between them as shown in Figure 5 (51 and 52 in Figure 5), and the current flowing through ylH2'L was investigated. The results are shown in FIG. 6, where the boron sensitivity of the contact compensation boron-containing region 43 is changed and the graph is plotted for each resistance value. As is clear from the figure, when the resistance value is low, that is, the elementary concentration is low, the voltage-current line is non-linear, that is, non-ohmic. I can see if it has become straight and ohmic.

コンタクトH4f曾貝不;純物頭域の形成力法は他の方
法によってもよい。例えは、卯(71Aを診照丁、bと
、p形シリコン基板71に11形きく域72を゛形成し
ンi後、先ず、絶縁膜と733辷形成し、慾し1]けし
一全面に窒化テクノ膜(にl−さ1500X程度)74
を被着する( ZK 7図(イ))。この屋化ナクン映
74の上からホウメtイオンを注入しく80 (kV)
 、 5 XI O”〔個/Cnl 、:l r深さ1
500 〔X〕)、電極窓を辿してn影領域72の電極
形成領域の表ノ曽部に筒没度ホウ素領域75を形成する
。その後、アルミニウム/シリコン層(厚さ1μ+f1
 ’4j)肢)76を椋21イし、・やターニングする
ことによって′に24組および自己、腺を形成する。
Contact H4f Zeng Kai Fu; Other methods may be used to form the pure head area. For example, after forming an 11-shaped listening area 72 on a p-type silicon substrate 71, first, form an insulating film 733, Nitride techno film (about 1500X) 74
(ZK 7 (a)). I want to inject HOMET ions from above this 80 (kV)
, 5
500 [X]), a boron region 75 is formed at the bottom of the surface of the electrode forming region of the n-shaded region 72 by tracing the electrode window. After that, aluminum/silicon layer (thickness 1μ+f1
'4j) Limbs) Form 24 pairs and self glands in ' by twisting 76 and turning slightly.

以上、窒化チタンを例にしてシリコン基;曾との電気的
コンタクトを補償する方法を述べてきたか、本発明が他
の高融点金属の屋化物一般を半41/i、基層に対して
電気的コンタクトを取る場合のコンタクト補償において
有意義であることは当業者には明らかであろう。
Above, we have described a method for compensating electrical contact with a silicon base using titanium nitride as an example, and the present invention has described a method for compensating electrical contact with a silicon base layer using titanium nitride as an example. It will be clear to those skilled in the art that this is useful in contact compensation when contact is made.

(6)発明の効果 1以上の秘H,+すJ7J・ら甲」らかなように、本発
明に依シ、1゛・カ触点金にの窒化物を牛者体基1曽と
直接pL触させかつオーミックなコンタクトとした先・
1引64造を翁ずろ半導体装置が提供ざ扛る。
(6) Effects of the Invention Secrets of 1 or more The point where the pL is touched and the ohmic contact is made.
Onizuro Semiconductor Devices will provide 64 pieces of equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図1は】1う常の電極窓の描込を示す断面図、第2
図はアルミニウム蜜俊を持つ半dソ体装■の部分−りr
面図、第3図はバリヤ金持つアルミニウム’CM 惨栴
ツタ、を示ずjiL来の半導体装置のF5ij分断au
図、第41z[は本発明の実施例を説明する工程順の半
導体装1th、!の部分H)[面図、&T5図は本発明
の実軸秒りの半導体装11)の試験方法を示す断面図、
第61iftンよその不占朱をまとめたグラフ、第7図
は本発明のもう一つの実施f・りを説ψ」する工程順の
半導体装置の部分〜r面図である。 11.21.31.41.71・=n形基板、12.2
2,32,42.72・・・p影領域、13゜33 、
44 、73・・・絶縁層、14,23,34゜36.
46.76・・・アルミニウムJ脅、35,45゜74
・・・す8!化ナタン/vy、43+ 75・・・コン
タクトイ111i¥高飯度ホウ素領植。 特J9出尉走人 富士ノJ株武芸召 特許出、妬代乃;人 升卯士 肖 木   朗 升九十 西 胎 和 之 ヅi:虐士  内  1) ¥  男 弁坤士 山 口 1・f3  之 第 1図 1′+ 第 2図 第3図 第 4図 第 5図 第 6図 1れ  月− 第7図 (イ) 5 (ハ)
FIG.
The figure shows a part of a semi-double body with an aluminum body.
The top view and Figure 3 do not show aluminum with barrier metal.
FIG. Part H) [Top view, &T5 is a sectional view showing the test method of the real axis second semiconductor device 11) of the present invention,
FIG. 7 is a graph summarizing the irregularities of various parts of the 61st case, and FIG. 11.21.31.41.71 = n-type substrate, 12.2
2,32,42.72...p shadow area, 13°33,
44, 73... Insulating layer, 14, 23, 34° 36.
46.76...Aluminum J threat, 35,45°74
...su8! Natan/vy, 43+ 75...Contact I 111i ¥ High degree of boron implantation. Special J9 rank runner Fujino J stock martial arts summons patent issued, envyyono; Jinshuuji Shōki Roushōku Nishi wata Kazunozui: Assassin 1) ¥ Otokobenkonshi Yamaguchi 1. f3 No. 1 Figure 1'+ Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 1 Moon- Figure 7 (A) 5 (C)

Claims (1)

【特許請求の範囲】[Claims] 1、半導体、l!i¥眉と接する高融点金属の窒化物か
らなる電極を有し、かつ前記半導体基層の前記電極と豪
する界面領域に電気的コンタクト補償のだめの高濃度不
純物領域を設けたことを特徴とする半導体装置。
1. Semiconductor, l! A semiconductor characterized in that it has an electrode made of a nitride of a high melting point metal in contact with the semiconductor base layer, and a high concentration impurity region for electrical contact compensation is provided in an interface region of the semiconductor base layer that contacts the electrode. Device.
JP5360083A 1983-03-31 1983-03-31 Semiconductor device Pending JPS59181571A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5360083A JPS59181571A (en) 1983-03-31 1983-03-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5360083A JPS59181571A (en) 1983-03-31 1983-03-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59181571A true JPS59181571A (en) 1984-10-16

Family

ID=12947367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5360083A Pending JPS59181571A (en) 1983-03-31 1983-03-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59181571A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174319A (en) * 1987-01-14 1988-07-18 Hitachi Ltd Manufacture of semiconductor device
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
JPH07263556A (en) * 1995-03-24 1995-10-13 Hitachi Ltd Semiconductor device
JP2007299753A (en) * 2006-05-01 2007-11-15 Fei Co Particle-optical device with temperature switch

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507430A (en) * 1973-05-18 1975-01-25
JPS56146232A (en) * 1980-02-27 1981-11-13 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5832415A (en) * 1981-08-20 1983-02-25 Sanyo Electric Co Ltd Reducing method of contact resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507430A (en) * 1973-05-18 1975-01-25
JPS56146232A (en) * 1980-02-27 1981-11-13 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5832415A (en) * 1981-08-20 1983-02-25 Sanyo Electric Co Ltd Reducing method of contact resistance

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174319A (en) * 1987-01-14 1988-07-18 Hitachi Ltd Manufacture of semiconductor device
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
JPH07263556A (en) * 1995-03-24 1995-10-13 Hitachi Ltd Semiconductor device
JP2007299753A (en) * 2006-05-01 2007-11-15 Fei Co Particle-optical device with temperature switch

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