JPS59180371A - Integrating ammeter - Google Patents

Integrating ammeter

Info

Publication number
JPS59180371A
JPS59180371A JP58053704A JP5370483A JPS59180371A JP S59180371 A JPS59180371 A JP S59180371A JP 58053704 A JP58053704 A JP 58053704A JP 5370483 A JP5370483 A JP 5370483A JP S59180371 A JPS59180371 A JP S59180371A
Authority
JP
Japan
Prior art keywords
circuit
voltage
signal
output
constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58053704A
Other languages
Japanese (ja)
Inventor
Shunichi Kobayashi
俊一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Tokyo Electric Power Co Holdings Inc
Original Assignee
Toshiba Corp
Tokyo Electric Power Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Electric Power Co Inc filed Critical Toshiba Corp
Priority to JP58053704A priority Critical patent/JPS59180371A/en
Publication of JPS59180371A publication Critical patent/JPS59180371A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To widen a dynamic range by inputting the output of a constant-multiple-voltage generating circuit to a comparator through a Miller integration circuit, opening and closing a switch by an output signal of pulse-width modulation, and leading in a signal proportional to current consumption. CONSTITUTION:A current transformer 11 performs conversion to the signal proportional to the current consumption of a feeder, and a pulse-width modulation type time-series multiplying circuit 12 inputs the signal under the on/off control of a switch circuit 124 and supplies it to an LPF13 with an integration function. A voltage obtained by integration is converted by a voltage-frequency converting circuit 14 into a pulse signal, which is counted to integrate the current. The circuit 12 is equipped with the constant-multipled-voltage generating circuit 121 which generates a constant multiple voltage, Miller integration circuit 122, and comparator A4 which compares and feed the output of the circuit 122 back to the circuit 122 and imposes pulse-width modulation upon the constant multiple voltage, and the circuit 124 is turned on and off according to the output signal of the comparator and its inverted signal. Consequently, the current is integrated with high precision even at the time of less loading and against a distortion wave.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、電a、を積算する8R算電流計の改良に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in an 8R calculation ammeter that integrates electricity a.

〔発明の技術的背景及びその間頂点〕[Technical background of the invention and its highlights]

従来、電流を積算する場合、入力電流を時分割乗算回路
を変形した全波整流回路で全波整流し、この整流出力を
積分して電流積算を行っている。第1図はその積算電流
計の全体構成を示す図であって、変流器Iによって給電
線の消費電流に比例した信号に変換した後、時分割方式
の全波整流回路2で全波整流し、この整流出力をローパ
スフィルタ3で積分して電流に比例する電圧信号に変換
し、さらに後続の電圧−周波数変換回路4で電圧に比例
した周波数のパルス信号に変戻して出力している。
Conventionally, when integrating current, the input current is full-wave rectified by a full-wave rectifier circuit that is a modified time division multiplication circuit, and the rectified output is integrated to perform current integration. Figure 1 is a diagram showing the overall configuration of the integrating ammeter, in which the current transformer I converts the signal into a signal proportional to the consumption current of the power supply line, and then the time-sharing full-wave rectifier circuit 2 performs full-wave rectification. This rectified output is then integrated by a low-pass filter 3 and converted into a voltage signal proportional to the current, and then converted back into a pulse signal with a frequency proportional to the voltage by a subsequent voltage-frequency conversion circuit 4 and output.

而して、変流器11全波整流回路2およびロー・クスフ
イルタ3は、具体的には第2図に示す通シであるが、特
に全波整流回路2はインピーダンス変換機能をもったオ
ペアングAJ、コンパレータA2+インバータX1およ
び4個のスイッチ81〜S4のブリッジ回路2aとから
なる。この全波整流回路2の動作について述べると、変
流器1で給電線の消費電流に比例した信号±eit−ブ
リッジ回路2aに供給するとともに、信号e、をオペア
ン7’AZに供耐する。このオペアンプAIは電圧フォ
ロワに構成して信号e7をインピーダンス変換した後、
この回路出力をコンパレータA2でt4ルスに変換して
いる。そして、第3図に示すように、信号十e3iの正
領域のときにコンパレークA2から”工″の論理信号を
出力してスイッチSl、S、をオンし、信号十eiの正
領域の信号を出力する。また、信号+e6の負領域のと
きにコンパレータA2の0”をインバータX1で反転し
て“1′″の論理信号に変快し、この信号を用いてスイ
ッチS1 。
Specifically, the current transformer 11, the full-wave rectifier circuit 2, and the low filter 3 are of the configuration shown in FIG. , comparator A2+inverter X1, and a bridge circuit 2a including four switches 81 to S4. To describe the operation of the full-wave rectifier circuit 2, the current transformer 1 supplies a signal ±eit which is proportional to the current consumption of the power supply line to the bridge circuit 2a, and also supplies a signal e to the operational amplifier 7'AZ. After configuring this operational amplifier AI as a voltage follower and converting the impedance of the signal e7,
This circuit output is converted into a t4 pulse by a comparator A2. Then, as shown in FIG. 3, when the signal 10e3i is in the positive region, the comparator A2 outputs a logic signal of "work", turns on the switches Sl and S, and the signal 10e3i is in the positive region. Output. Further, when the signal +e6 is in the negative region, the 0'' of the comparator A2 is inverted by the inverter X1 to convert it into a logic signal of 1'', and this signal is used to switch the switch S1.

S4をオンし、信号−eiの正領域の信号を出力する。Turn on S4 and output a signal in the positive region of signal -ei.

従って、全波整流回路2から第3図すのような信号、が
出力される。そこで、この全波整流回路2の出力を後続
のローパスフィルタ3で積分し直流電圧に変換した後、
電圧−周波数変換回路4でその電圧に比例した周波数の
パルス信号に変換して出力する。従って、このパルス信
号を計数積算すれば、電流を積算したことになる・ しかし、第2図のような全波整流回路2の場合、次のよ
うな問題がある。先ず、信号十〇iはオペアン7’AZ
、コンノ9レータA、?fパルスに変換されるが、これ
らのオにアン7’AI等にはオフセット電圧があるため
軽負荷の入力電流を適格に判定することは困難であシ、
かつリニャリティも悪くなる。また、信号十eiを直接
オペアンプA1等に入力しているためスイッチSl〜S
4の開閉制御はひずみ波(高調波)の影響を直接受ける
問題がある。また、オペアンプA1等に応答速度がおる
ため常に信号+〇iが遅れてスイッチ回路2aよ多出力
される問題がおる。さらに、オ(アンfA1等にオフセ
ット電圧があると、スイッチ81〜S4の開閉時間が短
かく、な9、第3図8の出力レベルが低下するので、電
圧−周波数変換回路4のダイナミックレンジがせまくな
る欠点がある。
Therefore, a signal as shown in FIG. 3 is output from the full-wave rectifier circuit 2. Therefore, after integrating the output of this full-wave rectifier circuit 2 with a subsequent low-pass filter 3 and converting it into a DC voltage,
A voltage-frequency conversion circuit 4 converts the voltage into a pulse signal with a frequency proportional to the voltage and outputs the signal. Therefore, if this pulse signal is counted and integrated, the current will be integrated. However, in the case of the full-wave rectifier circuit 2 as shown in FIG. 2, the following problem exists. First, signal 10i is operational 7'AZ
, Konno9reta A, ? It is converted into an f pulse, but since there is an offset voltage in these O and A7'AI etc., it is difficult to accurately judge the input current of a light load.
Moreover, the linearity also deteriorates. In addition, since the signal 10ei is directly input to the operational amplifier A1 etc., the switches SL to S
The opening/closing control of No. 4 has the problem of being directly affected by distorted waves (harmonics). Furthermore, since the response speed of the operational amplifier A1 etc. is limited, there is a problem that the signal +〇i is always delayed and multiple outputs from the switch circuit 2a. Furthermore, if there is an offset voltage in the amplifier fA1, etc., the opening/closing time of the switches 81 to S4 will be shortened, and the output level in FIG. It has the disadvantage of being small.

〔発明の目的〕[Purpose of the invention]

本発明は上記実情にかんがみてなされたもので、軽負荷
時およびひずみ波に対しても高精度に電流を積算するこ
とができ、しかもダイナミ、クレンソを広くとることが
可能な積算電流計を提供することを目的とする。
The present invention has been made in view of the above-mentioned circumstances, and provides an integrating ammeter that can integrate current with high precision even during light loads and distorted waves, and that can have a wide range of dynamics and displacement. The purpose is to

〔発明の概要〕[Summary of the invention]

本発明はミラー積分回路およびヒステリシスコンノRレ
ータヲ有シ、このヒステリシスコンパレータの出力をミ
ラー積分回路にフィードバックして自励発振回路を構成
するとともに、ミラー積分回路にはコンノJ?レータの
出力の定数倍の電圧を入力して/?ルス幅変調すること
によシ、・ぐルス幅変調時分割乗算方式によシ給電線の
消費電流に比例した信号を取シ込んで積分するようにし
た積算・電流計でちる。
The present invention has a Miller integrator circuit and a hysteresis converter R regulator, and the output of the hysteresis comparator is fed back to the Miller integrator circuit to form a self-excited oscillation circuit. Input a voltage that is a constant times the output of the regulator/? By pulse width modulation, the pulse width modulation time-division multiplication method is used to acquire and integrate a signal proportional to the current consumption of the power supply line.

〔発明の実施例〕[Embodiments of the invention]

第4図は本発明の一実施例を示すブロック図でおって、
11は給電線の消費電流に比例した信号に変換する変流
器、12μ・ぞシス幅変調形時分割乗算回路、13は積
分機能をもったローパスフィルタ、I4は電圧−周波数
変換回路である。
FIG. 4 is a block diagram showing an embodiment of the present invention.
Reference numeral 11 designates a current transformer that converts the signal into a signal proportional to the current consumption of the power supply line, a 12μ·cis width modulation type time-division multiplication circuit, 13 a low-pass filter with an integration function, and I4 a voltage-frequency conversion circuit.

而して、・クルス幅変調形時分割乗算回路12は具体的
には第5図のように構成されている。
Specifically, the Cruz width modulation type time division multiplication circuit 12 is constructed as shown in FIG.

e を出力する定数倍電圧発生回路121と、抵抗R3
、コンデンサCおよびオペアンプA3よpなシ、前記定
数倍電圧を時定数R3・Cで積分するミラー積分回路1
22と、この積分出力をコンパレートして論理信号″1
″又は′0#の電圧十〇 又は−〇 を出力するととも
に、そr            r の一部を抵抗R4を介してミラー積分回路122の入力
端にフィードバックするヒステリシスコy I? v 
−タA 4 (!: 、このコンノやレータA4の出力
を反転するインバータX2と、このインバータX2の出
力を抵抗R5a RBで分圧して電圧1 ±2%、を基準電圧としてヒステリシスコン・臂レータ
A4の反転入力端に供給する分圧回路123と、ヒステ
リシスコンパレータA4およびインバータX2の@1”
信号で閉成せられる4個のアナログスイッチ81〜S4
よシなるスイッチ回路124とで構成されている。
A constant voltage doubler generating circuit 121 that outputs e and a resistor R3
, a capacitor C and an operational amplifier A3, and a Miller integration circuit 1 that integrates the constant multiplied voltage with a time constant R3·C.
22 and this integral output, a logic signal "1" is generated.
A hysteresis controller y I?
- Inverter X2 that inverts the output of this controller or regulator A4, and the output of this inverter Voltage dividing circuit 123 supplied to the inverting input terminal of A4, hysteresis comparator A4 and @1'' of inverter X2
Four analog switches 81 to S4 closed by a signal
It is composed of a different switch circuit 124.

次に、以上のように構成された積算電流計の作用を説明
する。先ず、変流器11によって給電線の消費電流に比
例した信号上e4に変換した後、この信号上e(をスイ
ッチ回路124に供給する。このとき、パルス幅変調形
時分割乗算回路12は次のような動作を行っている。即
ち、定数倍電圧発生回路121から発生した定数倍電圧
を、ミラー積分回路122はヒステリシスコンAlレー
タA4の出力に基づいて時定数R3・Cで正方向又は負
方向の積分を行う。今、ヒステリシスコン/やレータA
4の出力が論理@1#のときの時間区間をt 、論理″
″0″′のときの時間区間をt、とすると、各時間区間
ta、tbにおけるミラー積分回路にこの積分出力ek
は、=−e。
Next, the operation of the integrating ammeter configured as above will be explained. First, the current transformer 11 converts the signal e4 into a signal proportional to the current consumption of the power supply line, and then supplies the signal e() to the switch circuit 124. At this time, the pulse width modulation type time division multiplier circuit 12 In other words, the Miller integration circuit 122 converts the constant multiplied voltage generated from the constant multiplied voltage generation circuit 121 into a positive or negative direction with a time constant R3·C based on the output of the hysteresis condenser Al regulator A4. Integrate in the direction.Now, use the hysteresis condenser/lator A
The time interval when the output of 4 is logic @1# is t, logic''
If the time interval at the time of "0"' is t, then this integral output ek is sent to the Miller integration circuit in each time interval ta, tb.
is =-e.

となる。becomes.

これによシ、1a、 1.を求めると、トする。よって
、ヒステリシスコンパレータA 4 ybhら出力され
るAルスデー−ティサイクルD。
To this, 1a, 1. If you ask for it, you will get it. Therefore, the A pulse data cycle D output from the hysteresis comparator A 4 ybh.

Dは、 となる。従って、このパルスデューティサイクDでアナ
ログスイッチS! 、S4をオンして信号eiを取込み
、また)9ルスデユーテイサイクルDをインバータX2
で反転後アナログスイッチS!+83をオンして信号e
iを取込み、ローパスフィルタ13で積分すれば、この
ローパスフィルタ13の両出力端には、 の出力が得られる。っまシ、電流±eiに比例した電圧
信号e  、e  が得られる。そこで、op    
 on 電圧−周波数変換回路14はそれらの電圧信置eo p
 r e o nを/Jルス信号に変換して出方する。
D becomes . Therefore, with this pulse duty cycle D, the analog switch S! , S4 is turned on to take in the signal ei, and the ) 9 duty cycle D is input to the inverter X2.
After reversing, analog switch S! Turn on +83 and signal e
If i is taken in and integrated by the low-pass filter 13, the following outputs are obtained at both output ends of the low-pass filter 13. However, voltage signals e and e that are proportional to the current ±ei are obtained. Therefore, OP
on voltage-frequency conversion circuit 14 converts those voltage signals eo p
It converts r e on into a /Jrus signal and outputs it.

従って、以上のような実施例構成によれば、オペアンプ
A3のオフセットは積分動作によって消去され、コンパ
レータA 4 Oオフ セy ) ij:反転入力端の
電圧によって消去されるばがシでなく、定数倍電圧をミ
ラー積分回路122でパルス変調しながら積分している
ので、軽負荷と全く無関係にスイッチ回路124を開閉
制御できる。また、ミラー積分回路122の時定数を高
くとれば、時分割乗算回路I2の乗算精度も向上し、ひ
ずみ波に対しても高精度に信号上e4を取込んで測定で
きる。また、従来のものはオフセット電圧によって全波
整流回路の出力が下カシ、電圧−周波数変換回路のグイ
ナミックレンノをせまくしていたが、本機器は定数倍電
圧によって乗算回路の出力を上げるようにしているため
、グイナミックレンゾを広くとることができる。
Therefore, according to the configuration of the embodiment described above, the offset of the operational amplifier A3 is canceled by the integral operation, and the offset of the operational amplifier A3 is not canceled by the voltage at the inverting input terminal, but by a constant. Since the doubled voltage is integrated while being pulse-modulated by the Miller integration circuit 122, the switching circuit 124 can be controlled to open and close regardless of the light load. Further, if the time constant of the Miller integration circuit 122 is set high, the multiplication accuracy of the time division multiplication circuit I2 is also improved, and it is possible to capture and measure the signal e4 with high precision even for distorted waves. In addition, with conventional products, the output of the full-wave rectifier circuit was lowered due to the offset voltage, making the output of the voltage-frequency conversion circuit narrower, but this device uses a constant voltage to increase the output of the multiplier circuit. Because of this, it is possible to use a wide range of Guinamik Renzo.

なお、上記実施例はヒステリシスコンパレータA4の出
力をミラー積分回路122にフィードバックする構成で
あるが、例えば第6図のようにコンパレータA4の出力
を2系統にわたってフィードバックし、その1つは第5
図と同様にミラー積分回路122にフィードバックし、
他の1つはカウンタ125を介して抵抗R3の入力端に
フィードバックする構成でもよい。カウンタ125を介
する理由は入力として時分割周波数よシ充分長いパルス
幅の信号をつくるためで、結果的にe がミラー積分回
路122に加わっていることになる。
The above embodiment has a configuration in which the output of the hysteresis comparator A4 is fed back to the Miller integration circuit 122. For example, as shown in FIG.
Feedback to the Miller integration circuit 122 as in the figure,
The other one may be configured to feed back to the input terminal of the resistor R3 via the counter 125. The reason for passing through the counter 125 is to create a signal with a pulse width sufficiently longer than the time division frequency as an input, and as a result, e is added to the Miller integration circuit 122.

〔発明の効果〕〔Effect of the invention〕

以上詳記したように本発明によれば、パルス幅時分割乗
算方式を用いたので、軽負荷時およびひずみ波に対して
も高精度に電流を積算でき、かつリニャリティも改善す
ることができる。また、電圧−周波数変換回路のグイナ
ミックレンゾを広げることができる積算電流計を提供で
きる・
As described in detail above, according to the present invention, since the pulse width time division multiplication method is used, current can be integrated with high precision even during light loads and distorted waves, and linearity can also be improved. In addition, we can provide an integrating ammeter that can widen the magnitude range of voltage-frequency conversion circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の積算電流計のブロック図、第2図は第1
図の全波整流回路の構成図、第3図は第1図および第2
図の動作を説明する図、第4図は本発明に係る積算電流
計のブロック図、第5図は第4図の1?ルス幅変調型時
分割乗算回路の構成図、第6図は乗算回路の他の例を示
す構成図である・ 11・・・変流器、12・・・・やルス幅変調形時分割
乗算回路、13・・・ローパスフィルタ、I4・・・電
圧−周波数変換回路、121・・・定数倍電圧発生回路
、122・・・ミラー積分回路、A4・・・ヒステリシ
スコンパレータ、I24・・・スイッチ回路、125・
・・カウンタ。
Figure 1 is a block diagram of a conventional integrating ammeter, and Figure 2 is a block diagram of a conventional integrating ammeter.
The configuration diagram of the full-wave rectifier circuit in Figure 3 is similar to Figures 1 and 2.
4 is a block diagram of the integrating ammeter according to the present invention, and FIG. 5 is a diagram explaining the operation of FIG. A block diagram of a pulse width modulation type time division multiplication circuit. Fig. 6 is a block diagram showing other examples of a multiplication circuit. Circuit, 13...Low pass filter, I4...Voltage-frequency conversion circuit, 121...Constant double voltage generation circuit, 122...Miller integration circuit, A4...Hysteresis comparator, I24...Switch circuit , 125・
··counter.

Claims (2)

【特許請求の範囲】[Claims] (1)給電線の消費′に流に比例した信号をスイッチ回
路の開閉制御によって取込んで積分し、この積分によっ
て得た電圧を周波数に変換する積算電流計において、定
数倍電圧を発生する定数倍発生回路と、この回路の定数
倍電圧が入力されるミラー積分回路と、このミラー積分
回路の積分出量をコン・gレートしてその出力をミラー
積分回路にフィードバックし前記定数倍電圧をノやルス
幅変調させるコン/にレータとを備え、このコンパレー
タの出力信号およびこの出力信号の反転信号で前記スイ
ッチ回路を開閉制御することを特徴とする積算電流計。
(1) A constant that generates a constant multiplier voltage in an integrating ammeter that takes in and integrates a signal proportional to the current consumption of the power supply line by opening and closing control of a switch circuit, and converts the voltage obtained by this integration into a frequency. A double generation circuit, a Miller integrator circuit to which the constant double voltage of this circuit is input, and a converter that converts the integral output of this Miller integrator circuit and feeds the output back to the Miller integrator circuit to obtain the constant double voltage. 1. An integrating ammeter comprising: a comparator/lator for modulating pulse width and pulse width, and opening/closing of the switch circuit is controlled by an output signal of the comparator and an inverted signal of the output signal.
(2)  定数倍発生回路はカウンタよシなシ、前記コ
ン/ぐレータの出力をカウンタに入力して定数倍電圧を
得ることを特徴とする特許請求の範囲第1項記載の積算
電流計。
(2) The integrating ammeter according to claim 1, wherein the constant multiplication generating circuit is not a counter, and inputs the output of the converter to the counter to obtain the constant multiplication voltage.
JP58053704A 1983-03-31 1983-03-31 Integrating ammeter Pending JPS59180371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58053704A JPS59180371A (en) 1983-03-31 1983-03-31 Integrating ammeter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58053704A JPS59180371A (en) 1983-03-31 1983-03-31 Integrating ammeter

Publications (1)

Publication Number Publication Date
JPS59180371A true JPS59180371A (en) 1984-10-13

Family

ID=12950213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58053704A Pending JPS59180371A (en) 1983-03-31 1983-03-31 Integrating ammeter

Country Status (1)

Country Link
JP (1) JPS59180371A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461073U (en) * 1990-10-04 1992-05-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461073U (en) * 1990-10-04 1992-05-26

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