JPS59178833A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To keep the relation of phase between a clock and an input signal constant by detecting the rate of mark of an input signal by a mark rate detecting means, and controlling the phase control means in response to this detected value. CONSTITUTION:An L or C of a BPF part of a BPF phase control circuit 12 is changed according to the mark rate to an input signal detected by the mark rate detecting circuit 15. That is, the control circuit 12 is constituted that a varactor diode Dv is connected in parallel with a capacitor C0 only and a reverse bias voltage Vx is given thereto in an equivalent circuit comprising a coil L0, the capacitor C0 and a resistor R0. Thus, the resonance frequency of the BPF is controlled by controlling the voltage Vx. Then, the phase after passing through the BPF is controlled by the Vx.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a clock recovery circuit, and in particular, the present invention relates to a clock recovery circuit, and in particular, it controls the phase of a recovered clock, which varies based on the mark rate of an input signal, to a predetermined level with respect to the phase of the input signal. The present invention relates to a clock recovery circuit that maintains a relevant state.

[Technology background]

A receiving circuit in a POM transmission or digital optical transmission system generally includes an 8σ positional amplification circuit, an equalization amplification circuit, an identification circuit, and the like. In the identification circuit, a system that simply identifies only the voltage, and a system that identifies the voltage while being synchronized with a reference clock signal have been considered. In this case, in the latter method, the phase relationship between the input signal to the separate identification circuit and the reference clock must always be kept constant.

On the other hand, as methods for obtaining the reference clock, (2) a method using a high-precision off-mirror, and (2) a method using one Pi and L oscillator.
(3) a method that uses a narrowband BPF (band pass filter);
This method requires a complicated circuit configuration and is technically difficult to achieve its purpose in a high frequency range. Therefore, when high transmission speed is required, narrowband BPF (3)
Extract the basic clock frequency from the transmission signal using
A method of regenerating the clock is appropriate.

[Problems with conventional technology]

FIG. 1 shows the configuration of a conventional clock recovery circuit using the BPF (3) above, where l is I! 2 is a BPF, 3 is a limiter amplifier, and 4 is a pulse width adjustment circuit. When regenerating a clock using this beat lock regeneration circuit, the phase of the regenerated clock is (1)
The relationship between the center frequency of BPF and the fundamental frequency of the clock, (
it) BPF passband width, GiD input signal phase,
It fluctuates in relation to the mark rate of 9 etc. of the amplitude 1M input amount of the 4ψ input person.

Here, the pulse occupancy rate of the input signal per unit time is called mark rate.

In this way, when the phase of the recovered clock changes according to the mark rate of the input signal of the clock recovery circuit, unless the mark rate of the input signal becomes about that of a bird, the phase of the recovered clock will change according to the mark rate of the input signal of the clock recovery circuit. Since the phase does not match, the identification function in the identification circuit will not work properly.

[Purpose of the invention]

The present invention solves this problem in view of the above problem, and by detecting and correcting the mark rate of the input signal, the phase of the reproduced clock that changes according to the mark rate of the input signal is adjusted relative to the phase of the input signal. It is an object of the present invention to provide a clock recovery circuit that controls the phase characteristics of a bandpass filter so as to maintain a constant phase relationship.

[Structure of the invention]

In order to achieve this object, the clock regeneration circuit of the present invention includes mark rate detection means and 1-phase control means in the clock regeneration circuit that extracts the fundamental frequency from an input signal, and detects the mark rate of the input signal. The present invention is characterized in that the phase relationship between the reproduced clock and the input signal is maintained constant by detecting the mark rate by means of a mark ratio and controlling the phase control means according to the detected mark rate value.

[Embodiments of the invention]

Before explaining the present invention in detail, the phase characteristics and frequency characteristics of the BPF will be explained. Generally, the BPF(7) equivalent circuit is represented by a west terminal network of a coil L, a capacitor C9, and a resistor R connected in series as shown in Figure 2.
As shown in FIG. 3(α)(b), when C or L of the BPF is changed, the center frequency fO changes and the phase characteristics for the same human signal frequency also change, so the BPF
Phase characteristics after passing can be controlled. That is, increasing fo causes the phase to advance, and decreasing fo causes the phase to lag. Therefore, the phase relationship between the input signal of the clock recovery circuit and the recovered clock is determined by using the above characteristics of the BPF.

It suffices if it does not change according to the mark rate of the input signal.

FIG. 4 shows the configuration of a clock recovery circuit according to the present invention.

In the figure, 11 is a separately installed amplifier, 12 is a band pass filter (BPF) phase control circuit, 13 is a limiter amplifier to keep the output amplitude constant, and 14 is a pulse width adjustment device, with the designation σ. Reference numeral 15 denotes a mark rate detection circuit for making the duty ratio of the reproduced clock amplified by the limiter amplifier 13 50%. In the embodiment of FIG. 4, preamplifier 10. IJ Mitter Amplifier 13. The pulse width fi4 adjustment device 14 corresponds to each circuit shown in 1.3.4 in FIG.
B according to the mark rate for the input signal detected in step 5.
L or O of the BPF portion of the PF phase control circuit 12 is changed.9 For example, if the phase advances due to an increase in the mark rate, change L or C to decrease fO, and the phase will be changed by decreasing the mark rate. If there is a delay,
Increase fo.

Whether the phase advances or lags due to mark rate fluctuations is determined at the time of circuit design. In this case, various methods can be considered for changing the BPF value, and one method is to use a variable capacitance diode to achieve the purpose.

FIG. 5 shows one embodiment in which the BPF phase control circuit [12 of FIG. 4 is realized. That is, in an equivalent circuit of a BPF in which a coil Lo, a capacitor Qo, and a resistor RO are connected in series, a variable capacitance diode DV is connected in parallel with only the capacitor CO, and a reverse bias voltage Vx is applied to it. Then, by changing the voltage of the variable capacitance diode, the year is changed. That is, let C be the combined capacitance of the capacitor CO and the capacitance tch of the variable capacitance diode l)v.

co10Cb Therefore, the series resonance frequency m fr of BPF is.

Generally, . Therefore, if the reverse bias pressure Vx for the nine-way variable diode Dv is changed.

Since the variable diode l)v'8'h changes according to well-known characteristics, fr can be controlled by controlling the separately mentioned voltage Vx. Therefore, the phase after passing through the BPF can be controlled by vx.

Figure 6 shows the BPF as a monolithic crystal filter (
An example will be shown in which the M.O.F.
The odd-value circuit of one crystal constituting the MOF can be expressed as shown in the off diagram, so by inserting a capacitor on the input side or output side of the MOF, 1
The center frequency fO of the passband of F can be changed. Namely.

FIG. 8 shows a basic configuration diagram when a MOF is used as a BPF. By inserting a desired capacitor C++02+03 or 04, the center frequency fO can be changed, so phase control can be realized.

Figure 9 shows that in the basic configuration shown in the OFF diagram, 1, for example, 01 on the input side is realized by a variable capacitance diode l)v, and the inductance L increases the high frequency impedance of the bias voltage Vx and has an effective function. It's set.

In addition, among the methods of changing L or C of the BFP in the embodiments of the present invention described above, for changing C, an example was shown in which the capacitance is effectively changed using a variable capacitance diode. , C1L may be changed manually, or the pitch of the coil L may be changed.

As described above, the BPF phase control circuit 12 in the circuit of FIG. 4 can be constructed. In addition, the fourth
It is clear to those skilled in the art that in the clock regeneration circuit according to the present invention shown in the figure, the mark rate detection circuit 15 can be easily realized by one, for example, an integrating circuit.

〔Effect of the invention〕

As is clear from the embodiments described above, in the clock recovery circuit according to the invention, even if the mark rate of the input signal changes, the phase relationship between the input signal and the recovered clock is maintained constant, and the phase relationship between the input signal and the recovered clock is maintained constant. The phase can also be easily controlled.

[Brief explanation of the drawing]

Figure 2 is an equivalent circuit of BPF, Figure 3 (α) and (h) are transmission and phase characteristic diagrams with respect to frequency, and Figure 4 is a diagram of the clock reproduction circuit according to the present invention. Example, Fig. 5 is the first large example of the BPF phase control circuit part in Fig. 4, Fig. 6 is an example of a BPF using MOF, OFF Fig. is a crystal value circuit, Fig. 8 is is M OF
FIG. 9 is a basic configuration diagram of a t3PF phase control circuit using the t3PF phase control circuit, and FIG. 9 shows an example of Kazuo implementing FIG. 8. In the figure, 11 is a preamplifier, 12 is a BPF phase control circuit,
13 is a limiter amplifier, 14 is a pulse width A adjustment circuit, 15
mark rate detection circuit, not shown respectively. Patent tOB applicant Fujitsu Ltd. agent Akira Yamatani Patent attorney Figure 6 Figure 7I'] C3 No. 8 (21 V

Claims (1)

[Scope of Claims] t. A clock regeneration circuit that extracts a fundamental frequency determined by the transmission speed of an input signal and regenerates a clock, comprising a mark rate detection means for detecting a pulse occupancy rate of the input signal per unit time, and a mark rate detection means for detecting the pulse occupancy rate of the input signal per unit time; 1. A clock regeneration circuit comprising: phase control means for controlling to maintain a constant phase relationship between the clock reproduced according to the pulse occupancy rate detected by the rate detection means and an input signal. 2. The clock regeneration according to claim 1, wherein the phase control means is a bandpass filter, and the phase of the regenerated clock can be controlled by changing the center frequency of the bandpass filter. circuit.