JPS59178690A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To obtain a sample holding circuit which is suitable for sample holding from low speed to high speed with a simple constitution and make phase compensation unnecessary by processing the control of sample holding with a digital signal. CONSTITUTION:The start and the stop of oscillation of an oscillator 17 are controlled by a control signal 18, and monostable multivibrators 19 and 20 are triggered by the output of the oscillator 17. The output voltage of a switching element whose turn-on/off is controlled by the output of the vibrator 19 is stored in a capacitor 23, and the output of the vibrator 20 controls turn-on/off of a switching element 22, and the electric charge in the capacitor 23 is discharged when it is turned on. Emitter follower circuits 24 and 25 to which the output of the element 22 is inputted are provided, and an input signal as a sample holding object is impressed to the input of the element 21, and a sample holding output signal is taken out from circuits 24 and 25.

Description

[Detailed description of the invention] Industrial applications The present invention relates to sample and hold circuits.

1 shows a conventional embodiment. FIG. 2 shows sample-and-hold waveforms by the sample-and-hold circuit shown in FIG. 1. First, the circuit operation in the 4$1 diagram will be explained for each period A to D.

[Sample/hold period A]

During this period, the waveform change of the input signal (1) to be sampled and held is in an increasing state. During the sampling period Tl of the sample-and-hold control signal f (9), the cathode of the diode (2) has a voltage value of Vcc, and the diode (2) is turned off. J (hereinafter referred to as FET)
4), and the FET (4) becomes conductive.

Therefore, the sample signal is input to the non-inverting input ■ of the operational amplifier (3).
The hold target input signal (1) is input, and the operational amplifier (
3) and (5), and a sample-and-hold output signal (6) is output to the output terminal (7). Also, 1 at the inverting input e of the operational amplifier (3) and the inverting input θ of the operational amplifier (5)! J: Valley η chain hold output value (6)
Although a part of the field is field-nopec
) (5) tri: Since it has infinite amplification, VCa is set so that the voltage difference between the non-inverting input ■ and the inverting input O becomes almost zero volts for both op-amps j (3) and (5).
The output is the target input signal (1).
A waveform almost similar to that is output. The capacitor (8) is charged with a voltage during a period TI corresponding to the pulse length of the human input signal (1) to be sampled and held. Next, sample baud 15 de ] ] human 0 - Louis number ° 9
) of 1 node Akima T2, tiode (2)
The cathode voltage of decreases, and the diode (2) becomes ONL,
The gate voltage of FET (,i) decreases, and FET (4
) is turned OFF. Therefore, during the period T, the voltage charged in the capacitor (8) is used as a hold voltage, and almost the same voltage as this hold voltage is output to the output terminal (7) of the operational amplifier (5). Since the operation is general, it will be omitted). Therefore,
During the entire period T, the sample hold period A in Fig. 2
As shown in , an output waveform that is almost similar to the target input signal (g) of the sample-and-hold circuit is obtained. Sample bold periods B1 and C are the same as period A in operation.

[Sample/Hold Period D] During this period, the waveform change of the input signal (1) to be sampled and held is in a decreasing state. Sample hold period A, B
, C as well as the sample and hold control signal.
In the sample period T, of W (9), the diode (
2) OFF L, voltage is applied to the gate of FET (4), and FET (4) becomes conductive. Therefore, when the voltage of the input signal to be sampled and held (1) decreases due to the operations of the operational amplifiers (3) and (5) as described above, the output of the operational amplifier (3) decreases to approximately the same voltage. At this time, the voltage of the capacitor (8) is higher than the output voltage of the operational amplifier (3) because it is the voltage before the sample-and-hold target a''8' (1) is applied. ) is zero, so the charge on the capacitor (8) is discharged towards the output of the operational amplifier (3) in a trench that is equal to the output voltage of the operational amplifier (3), and the electric charge is transferred to the output terminal (7). The waveform that is almost the same as that of the input signal to be sampled and held (1) is output.'I'2
In the interval, the voltage of the capacitor (8) is held by the same operation as explained in the Nj interval A, and almost the same voltage as this voltage is output to the output terminal (7).

Therefore, during the entire period T, as shown in the sample and hold period DK of FIG. 2, an output substantially similar to the input signal (1) to be pulled and held is obtained.

In addition, in Fig. 1, the resistance (IQ is op amp'j (3
) with a large resistance p added to the input of the protective resistor, capacitor ゛θ1) and resistor (Yuke, capacitor (8)
This is to compensate for the phase delay caused by 'a. resistance(
7314) is a resistor that determines the amplification degree of au pair-7j (3), and resistor 0υ is a bias resistor of the gate of FET (4).

However, the conventional sample-and-hold circuit has the following problems.

0 For high-speed sample and hold, a high-speed operational amplifier is required, resulting in an expensive circuit.

0 In order to design analogically, the resistor 1 (1
It is difficult to set i. The circuit configuration is complicated. 0 It is difficult to perform phase compensation (oscillation is likely to occur).

OBJECTS OF THE INVENTION An object of the present invention is to provide a sample-and-hold circuit that can reliably perform sample-and-hold processing from low speed to high speed with a simple configuration and using a gain signal.

Structure of the Invention The sample-and-hold circuit of the present invention includes an oscillator, a control means for controlling the start and stop of oscillation of the oscillator, and a first monostable multivibrator (g2) which is trigged by the output of the oscillator. , a first switching element whose on-off is controlled by the output of the first monostable multivibrator, a capacitor that stores the output voltage of this first switching element, and an output of the second monostable multivibrator. A second switching element that discharges the charge in the on state is controlled, and an emitter holo-9 circuit whose input is connected to the output of the second switching element is provided, and a susceptor is connected to the input of the first switching element. - It is characterized by applying an input signal to be held and extracting a sample and hold output signal from the output of the circuit.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 3 to 6.

When a sample start signal OQ is input to the microcomputer Qi'9 as a control device, the microcomputer (1υ) recognizes this signal and outputs an operation start signal 08 to the oscillator θη. The oscillator starts operation using this control signal (old).When the output signal of the oscillator (17) is input to the monostable multi-byte generator OI (hereinafter referred to as monostable multi), the monostable multi-vibrator (hereinafter referred to as monostable multi) is activated. ) and output sample-and-hold control signals (■) and [F]), respectively, which have a relationship similar to that of the fourth worst. These two signals (during IJ) are mutually synchronized signals.

During the sample period T+ of the sample-and-hold control (I), the signal (I) is at logic level ゝゝ■(''
Therefore, the transistor υ is turned on, and since the signal (IT) is at the logic level XゝL'', the transistor (a) is turned off. Therefore, the capacitor (to) is turned off.
Since is a sufficiently small time constant with respect to the sample period I, it is charged to approximately the same voltage as the input signal (1) to be sampled and held. Next, in the hold period T2, since the signal (I) is "L", the transistor (2) is turned off, and since the signal (I) is "L", the transistor (A) is turned off. Since the output side of the capacitor @ is connected to a 1-3 follower circuit composed of a transistor (product) and a resistor (c), the output impedance is high and the voltage of the capacitor +1@ is held. Furthermore, in the discharge period T3, since the signal (I) is "L", the transistor voltage υ is turned off, and the signal (I) is turned off.
is present, so the transistor I turns on. Therefore, the charge on the capacitor (I) is discharged by the transistor (A) in preparation for the next sample-and-hold signal. In this way, during the entire period T, the As shown in the sample hold period A in Fig. 5, a waveform approximately equal to the input signal (I) to be sampled and held is repeatedly output to the output terminal (A).Sample and hold period B in Fig. 5, Ct
The operation is the same as that of period A.

Figure 6 (a), (b), (c), and (d) are the control signal (to), the output signal of the oscillator (a), and the sample signal, respectively.
Hold Control Faith'! -(I) (II), (e) and (f) are transistors FAT), @ON-
OFF operation, (g) (h) (i) represents the short period, hold period, and discharge period of the capacitor (a). Also, Tof represents the generation time of the start signal 00.

In the embodiment described in L, a microcomputer was used as a control device for the oscillator U power, but this can be done simply by turning on and off the oscillator 1117).According to the switch circuit, sample and hold control can be performed digitally. Since it can be processed using signals, the following effects can be obtained compared to conventional processing using analog signals.

O High-speed sample-and-hold does not require high-speed operation-up unlike conventional methods, so it is inexpensive.

0 Suitable for sample and hold from low speed to high speed, and its circuit design is easy.

O There is no need for phase compensation as in the conventional case.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional sample-and-hold circuit;
The figure shows the sample/hold target signal and the sample/hold control signal in Figure 1.
3 is a diagram showing the relationship between hold output signals, FIG. 3 is a configuration diagram of an embodiment of the present invention, and FIG. 4 is a waveform diagram of the main part of FIG. 3. Figure 5 is a diagram of the relationship between the sample-and-hold target signal and the sample-and-hold output signal for the sample-and-hold control signal in Figure 3, and Figure 6 is a diagram of the relationship between the sample-and-hold control signal in Figure 3 and the sample-and-hold output signal.
FIG. 3 is a waveform diagram of main parts of a hold circuit. (1)...Input signal to be sampled and held, (6)
...sample/hold output signal, q average...microcomputer [control device], αQ...start signal, 0
7) ...Oscillator, 0 flaw (a) ...monostable multi [first and second monostable multivibrator], (Foundation) (a)
...Transistor [first and second switching elements], wire...capacitor, (c) (b)...transistor and resistor that constitute the emitter follower circuit Fig. 1 Fig. 2 Fig. 3

Claims (1)

[Claims] 1. An oscillator, a control means for controlling the start and stop of oscillation of the oscillator, first and second monostable multivibrators which are trip-powered by the output of the oscillator, and a first monostable multivibrator. A first switching element whose on-off is controlled by the output, a capacitor that stores the output voltage of the first switching element, and a second monostable multivibrator whose on-off is controlled by the output of the first switching element and is in an on state. A switching element @2 that discharges the electric charge of the capacitor and a circuit whose input is connected to the output of the second switching element are provided, and the input of the first switching element is connected to the sample/hold target. Apply the input signal and sample from the emitter holo 9 circuit output.
Sample and hold circuit that extracts the hold output signal.