JPS59178687A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a capacitor by allowing power source voltages of a precharging circuit and an active restore circuit to follow up the potential of the counter electrode of the capacitor. CONSTITUTION:A potential V'CC is changed with a value which is shifted from a potential OP by the threshold voltage of a depletion transistor TR Q12. In the stand-by mode, the power source voltage of a precharging circuit PRC is V'CC, and consequently, potentials of bit line BL and BL' are V'CC also. When the selection mode is set, potentials of bit lines BL and BL' fall from the reference V'CC. When the sense mode is set, the potential of the bit line BL' having a lower potential falls to 0. When the restore mode is set, the potential of the bit line BL having a higher potential rises to V'CC at most. Thus, potentials of bit lines do not exceed V'CC in any case, and consequently, the potential of a node N1 does not exceed V'CC. As the result, a voltage higher than V'CC is not applied to an insulating film of the capacitor in a memory cell.

Description

TECHNICAL FIELD OF THE INVENTION The invention relates to conductor storage devices, and more particularly to MIS dynamic random access memories (RAM) having one transistor, one capacitor type memory cell.

Technical background: In MIS dynamic RAfVi, a one-transistor, one-capacitor type memory cell is used, which is advantageous in terms of the degree of integration. This memory cell consists of a transistor having a source (or drain) connected to a bit line and a gate connected to a word line, with the drain (or source) of this transistor and 'I' held at a predetermined potential as poles. It is equipped with a capacitor composed of: In this case, in the capacitor, if the impurity diffused N in the semiconductor substrate that acts as the drain of the transistor is used as one electrode, and the electrode that holds the above-mentioned Pf+ foot potential is used as its opposite electrode, there is a gap between these two electrodes. A thin insulating film, such as an oxide film (stot), is formed. and,
The information is expressed by whether or not charge is accumulated in the capacitor of the information @1'' or 0#.

The counter electrode of the capacitor of the above-mentioned memory cell usually has a
Power supply voltage■. C or ■88 is applied, but recently the total voltage (Ve(! -vBB)) applied to the counter electrode
/2 may be used to reduce the size of the capacitor surface.

In this case, since there is a margin in the withstand voltage of the capacitor insulating film, the thickness of the dividing film can be reduced, and as a result, the capacitance per unit area of the capacitor increases. For example, if the thickness of the P film is set to '&', the capacitor required to obtain the Pfr leg capacity will be nearly half that of the conventional one. Tsu1v
This provides an effective means for reducing cell volume and weight due to miniaturization of a single device.

PRIOR ART AND PROBLEMS In the conventional dynamic RAM, the potential Vcc/2 (V8820) is applied to the opposite terminals of all capacitors.
As a means for generating the above-mentioned potential Vc, /2, (3
) A voltage dividing (b) path that divides VQQ is used.The resistance value of the voltage dividing N path is set to be quite large, for example, several tens to hundreds of ohms, in order to keep the standby current low. Therefore, when the power is turned on, the potential of the opposing electrode of the capacitor of the memory cell is Vc.

It will start up quite late compared to .

On the other hand, the precharging circuit that precharges the pit line potential sets the pit and B potentials to V. 0, and the active restore circuit raises the higher bit line potential with Vcc, but after the power is turned on, Vo. is the belonging value, for example 5v
When the bit line potential 'I rises, the precharging circuit
It is possible to precharge with the kVoc reed and also use the active restore circuit to raise the higher bit line potential to Vcc.

Therefore, when the power is turned on, even though the potential of the opposing polarization of the capacitor is at a low level compared to Vcc, the potential of the transistor side electrode of the capacitor is Vcc.
cK may occur. Since this M, the insulating film of the capacitor has almost V. A voltage of C will be applied. However, in this case, the maximum withstand voltage of the P2 membrane of the capacitor (4) is V. , /2, so a voltage exceeding the maximum withstand voltage will be applied to the membrane at this moment. There is a problem that the membrane may be destroyed.

Purpose of the Invention The purpose of the present invention is to solve the problems of the conventional type described above.
Pit a'# where the precharging circuit precharges
Add the pit line potential raised by the 1st place and active restore circuit to the potential of the opposing electrode of the memory cell capacitor @
By doing so, the voltage applied to the capacitor of the memory cell is prevented from greatly exceeding the designed applied voltage value Vco/2 even when the power is turned on, thereby preventing damage to the capacitor Mk.

Structure of the Invention In order to achieve the above-mentioned object, according to the present invention, first. a second power supply means, a plurality of word lines, a plurality of pit lines,
1 provided at each intersection of the pit line and the word cave
Transistor 1 capacitor type memory cell and front 8
Pi 1st. A voltage dividing means is provided for dividing the entire supply potential difference of the second power supply means and applying the divided voltage to the opposing electrode of the capacitor of the memory cell, and the potential supplied to the bit line is controlled by the output of the voltage dividing means. A semiconductor memory device is provided.

Embodiments of the Invention The present invention will be described below in comparison with a conventional type with reference to all the drawings.

FIG. 1 is a circuit diagram showing a conventional semiconductor memory device. In FIG. 1, memory cell MC+ is provided at the intersection of word line WL and bit line BL, and memory cell MC+ is provided at the intersection of word line WL and bit line BL.
It is provided at the intersection of the ij word line WL and the bit iBL. Memory cell MC,.

MC2 is transistor Q+, Qt and capacitor CI
, Ct.

The nodes Nr and Nt on the transistor side of the capacitor CI+C3 of the memory cells MC+ and MCt are formed by an impurity diffusion layer in the semiconductor substrate, while the counter electrode formed between the insulation layers is connected to the power supply voltage (2). The potential is held at 1/2 of that of C. That is, the resistance R+ −Re (R+
= R2) is the output potential O of the voltage divider circuit VD.
P is applied to the upper and opposite electrodes. Also, 'power supply' tortoise pressure V. In order to suppress power consumption due to C, resistors R, ,
The value of R is minimized to several tens to hundreds of Ω. In addition,
Other word lines and other pin HM pairs also exist, but are not shown. In addition, all the bit and node lines are connected to one dummy cell in addition to the original memory cells, and these dummy cells are connected to the bit line BL group, the bit line BT, and the dummy word line provided for each group. However, dummy cells and dummy word lines are also omitted in the figure (11115).

BT, f3L are connected to the precharging circuit PRC, the active restore circuit MALζE1, and the sense amplifier circuit SAK. Here, the preacher 2 fufu circuit PRC and the active restore circuit A
RE is turtle*<' pressure V. . )It is connected to the.

Bricharging circuit PRCir, l' transistor Q3
Q4, in standby mode,
When clock signal BP goes high (BP>Vcc+Vt
h: However, Vth is the direct voltage of the enhancement type transistor), transistors Qs and Q4B are both on, and therefore bits) dBL and BL are both v
Precharged to cc.

In addition, the active restore circuit ARK is a transistor Q.
, ~Q8, are capacitors C, , C, and when the clock signal AR goes high in the restore mode (
AR>Vc, +Vth), the potentials of capacitors C3 and C4 rise. At this time, either the potential of pin H61BL or BL is V. c” If the voltage is higher than thh, transistor Q5 or Q♂ will be cut off, and therefore,
The potential of node N3 or N4 becomes equal to or higher than Vcc+v,h. Line B
Either L or BL is V. We will return to C.

The sense amplifier circuit SA includes transistors Qo and Qto kW L that constitute a flip-flop, and the operation of the sense amplifier circuit SA is based on the clock signal in the sense mode.
1': This is done by setting LETh high and turning on transistor Q++t''.

(7) The entire operation of FIG. 1 will be explained with reference to FIG.

Figure 2 shows the pressure V. The figure shows when 0 is input. That is, time 1. , the negative voltage Vc.

When Voc is turned on, VOC quickly rises and reaches a predetermined value, for example, 5V at time t1, whereas the rise of the potential OP of the VOC is extremely slow due to the large resistance value of the voltage divider H1 path VD. It's late.

When the voltage Vcc becomes stable after time t1, the refresh:L@ operation is started by the row address strobe signal RAS and ends at time t. In addition, the signal RAS
m11# is performed by an external loop circuit.

At time t3, the pit line precharging signal BP
When changes from high to low, it moves from standby mode to selection mode. This result, for example, the word line WL,
The potential of increases and transistor Q1 turns on,
Memory cell M C+ is selected. At this time, if the charge before the capacitor C8 of the memory cell MC is 0, then
The potential (8) of the bit line BL decreases in accordance with the capacitance of the capacitor C8 and the bit HBL. On the other hand, the bit @BL is lowered by a reference level provided between the bit line levels when reading the information "'1" and 10# cells due to a dummy cell (not shown). In this way, a small potential difference between the bit lines BL, BL is generated. Note that, conversely, memory cell MCI
If capacitor C1 is charged, the potential of iBL becomes higher than the potential of bit line BL.

Next, at time t4, when the clock signal LE changes from low to high, the sense mode is entered and the sense amplifier circuit SA operates. Tsuashiri, beep)) IIBL, B
The potential difference between L is amplified. At this time, the lower potential, the potential of the open bit line BL, decreases to 01.

Next, at time t, the clock signal Af? , is O to V. cK changes, and as a result, the active restore times g
ARE starts and enters restore mode.

At this time, the higher potential, the potential of the pinch bit line BL, is V. Return to o. Therefore, the potential of node N1 is also vcc'
Return at 1'.

That is, as shown in Fig. 2, the potential O of the opposing 'α
Even though P is still close to O, the potential of node N1 is V. C, and the insulating film of capacitor C1 has approximately Vcc.
This poses a problem in that the voltage applied to the rice polishing and the insulating film may be destroyed.

FIG. 3 is a circuit diagram showing an embodiment of the semiconductor device according to the invention, in which a depletion type transistor Q12 is added to the 1ψJ path of FIG. In this transistor Q+2, the power supply voltage Vcc is applied to the drain, the potential OP of the counter electrode is applied to the gate, and the voltage Vcc' at position 'α' is applied to the charging circuit P.
Acts as a power source for the RC and active restore path ARE. Potential V. 0' is vcc'-vG-Vt
h(d) = Vo+I Vth(dl l ・(
Sudashi V. is the gate 'm level, that is, the potential 0P1Vjh
(d) i'l: depression type transistor Qst
is the threshold voltage (negative value) of . Therefore, under the same conditions as described above (1, memory cell M C
, the best capacitor CI! The voltage applied to the membrane is Vo-1v, h(d) I-V.

=lVth(dl...(
2), destruction of the insulating film can be prevented by designing lv, h(a)l to be lower than the dielectric strength voltage of the capacitor.

For example, the normal value of vcc is all 5V, and Rs = R
2, then V in a stable state. = 2.5V. Of course, at this time, the voltage Vcc' must also be 5V, so from equation (1), l Vth(d) I = 2.
It will be designed to be 5 V.

The NW&operation' in FIG. 3 will be explained below with reference to FIG.

The potential Vcc' is the threshold voltage I Vth (d) I of the depletion type transistor Q+t with respect to the potential OPK.
It changes by the value shifted by . Therefore, if the potential OP is approximately O, Voc' is approximately I Vt at time t and thereafter.
h (d) remains at 1.

In the standby mode before time t3, the precharging circuit PRCI7) electrolytic voltage decreases at Vd, and therefore the potential of B L and B L also becomes Vc; When entering the mode, the bit line BL
, BL decrease with respect to Vcc' as in the case of FIG.

At time t4, when the sense mode is entered, the potential of the lower bit line BL drops to zero.

Even if the restore mode is entered at time t, the potential of the cylindrical bit line BL rises only to UVcc'!.

In this way, the potential of pin)[BL, BL will never exceed Vcc' in any case, and therefore the potential of node N
The potential of 1 will not exceed Vc (? Violet. This MAL
As in mli, a voltage higher than I V, h(d) 1 is not applied to the insulating film of the capacitor in the memory cell.

According to the detailed description of the invention, the capacitor is
Blicharging (b) path and active restore 1 circuit power to the potential of the turtle! Since it follows the voltage,
Even if the voltage of the opposite electrode is low when the power is turned on and the wire-cutting operation is performed, excessive voltage is not applied to the capacitor's insulating film, thus preventing breakdown of the insulating layer. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the entire conventional conductor memory device, FIG. 2 is a timing diagram for explaining the entire circuit operation of the device in FIG. 1, and FIG. 3 is an embodiment of the semiconductor device according to the present invention. FIG. 4 is a timing diagram for explaining the circuit operation of the device shown in FIG. 3. Voo: first power supply means, Vss (=O): second power supply means, BL violet, WLt
: word line, BL, BL: bit line, ■D: voltage dividing means, PRO: precharging means, ARE near active restore means, Q+t: depletion type transistor (potential following means).

Claims (1)

[Claims] 1. 1. a second 'Iit source supply means, a plurality of word lines, a number of bit lines, a one-transistor one-capacitor type memory cell provided at a valley intersection between the bit line and the word line, and i'iiJgselfi1 , i2 is provided with voltage dividing means for dividing the difference in potential supplied by the power supply means and applying it to the opposing electrode of the capacitor of the memory cell, and controlling and suppressing the potential supplied to the bit line by the output of the voltage dividing means. A semiconductor storage device designed to 2. A depletion type transistor metal fitting IS L,g transistor for controlling the potential supplied to the bit line has a drain connected to the first power supply means ffrJ, and a gate connected to the output of the voltage dividing means; 2. The semiconductor memory device according to claim 1, further comprising a source that generates a potential to be supplied to the front ruby focus.