JPS59178561A - Bank controlling system - Google Patents

Abstract

PURPOSE:To enable widening of common area and improve efficiency of use of memory by providing a bank number holding device that holds bank number, a decoder and a bank selection address gate. CONSTITUTION:Bank 0-bank 7 of 32K unit are formed in a memory module 31 and bank 0 is used as a common area. Similarly, bank 8-bank 15 of 32K unit are formed in a memory module 32. When address of a processor 30 is 0- 32K-1 address, area of bank 0 of the device 31 is accessed regardless of content of a bank register 33. In the case of 32K-64K-1 address, access is made to address part of the bank 1. Thus, as the bank 0 becomes a common area, and the bank 1 and succeeding are set to the device 33, the common area can be made wider and efficiency of use of memory can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory bank control system, and particularly to a memory bank control method that enables a processor operating in an instruction prefetch method to accurately execute a prefetch instruction even when switching banks. , relates to a device configured to make effective use of memory.

[Technology background]

When trying to satisfy various demands on a computer system,
The number of processor programs used in the computer system increases. Then, the program may grow larger than the address space that can be expressed by the processor.

A processor's address lines are usually determined by the processor's architecture, so increasing the address lines.

We were forced to change the architecture of the programs and program modules that we had developed up until then.

Program development tools become unusable. Therefore, a memory bank method is available as a method for expanding the program area without changing the processor architecture.

[Prior art and problems]

Usually, the bank system is constructed as shown in FIG. In the figure, 0.1...N are banks configuring the memory, each memory member of each bank 0, 1...N has a capacity that can be designated by the processor 10, and banks 0.1...N The selection is made by the decoder 12 decoding the bank number set in the bank register 11.

The system shown in FIG. 1 is very effective for processors that do not prefetch instructions.

However, for a processor designed to prefetch instructions so as to perform data processing at high speed, the configuration shown in FIG. 1 cannot be used for the following reasons.

That is, as shown in FIG. 2(a), when executing the contents of address n of bank BO, address n-1-1 is accessed and read in advance because of the instruction prefetch system.

By the way, when the content of address n is a bank switching command for bank B1, the access destination will be shifted to bank B1, and correctly, control will be performed based on the command at address n+1 of bank B1. However, the prefetch instruction is a jump instruction to address m, and bank B1
If the instruction at address n+1 is a jump instruction to address l.

What should normally have been a jump to l ends up jumping to m due to the prefetching of the instruction, and the correct operation cannot be performed in this case. To do this, for example, the address next to the bank switching instruction should be stored with a common instruction for each bank, or the next address after the bank switching instruction must be NO.
It would be possible to take countermeasures such as adding a P command, but this would limit its use.

Therefore, in a processor that prefetches instructions to perform high-speed processing, the bank switching instruction has conventionally been stored, for example, in the common section C of bank O, as shown in FIG. This common section C also includes a monitor central section that controls bank switching, common resources for each bank, and the like.

In the system shown in FIG. 6, memory modules 20 to 2
2, the memory module 20 has a bank 0 and a common section C, the memory module 21 has a bank 1, and the memory module 22 has a /(bank N). The selection of N is made in the bank register 23.
The decoder 24 decodes the Cunk number (set in The memory module 20 is controlled to be selected.

Therefore, in the conventional link system as shown in FIG.
There is a drawback that the memory usage efficiency deteriorates because the area becomes unused. Therefore, in order to use memory effectively, it is necessary to minimize the wasted area by making the common part C small, even though the common part C includes the monitor core described earlier. Met. This results in the disadvantage that it is difficult to use in terms of programming.

In addition, the determination by the address determination unit 25 requires a large number of bits to determine the address within the link, and it takes time to obtain the determination result.
This slows down the processing time, necessitating a longer machine cycle, and reducing the throughput of the data processing device.

Furthermore, in the system shown in FIG. 3, the memory module 2
Since 0, 21, and 22 each correspond to one bank, the space of the memory module cannot be made larger than the space that can be expressed by the processor address. This is because today, the degree of integration of memory devices is increasing day by day.
Since it is necessary to use memory that is limited to the processor address forever, it continues to have the disadvantage that the mounting area cannot be reduced forever.

[Purpose of the invention] The object of the present invention is to remedy these drawbacks.

By increasing the common area, eliminating unused areas, improving memory usage efficiency, and not reducing machine cycles, and making it possible to have multiple banks in the same memory module, the integration of memory elements increases. It is an object of the present invention to provide a bank control method capable of constructing a bank system that can reduce the mounting area.

[Structure of the invention]

In order to achieve this object, the bank control method of the present invention includes one or more memory modules and a plurality of banks provided in this memory module in a data processing device having a plurality of banks and a processor that constitute a memory. , a bank number holding means for holding a bank number, and a decoder.

Bank selection address gate means is provided, and when the most significant bit of the processor is a specific value of 1 or zero, the bank selection address gate means has a zero output, and otherwise the bank number is held in the bank number holding means. The bank is characterized in that the bank is selected according to the data obtained.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 4 and 5.

FIG. 4 is a block diagram of one embodiment of the present invention, and FIG. 5 is a memory map.

In the figure, 60 is a processor, 31.32 is a memory module, 33 is a bank register, 64B decoder, 40
~A3 is the Andei Gate.

Processor 60 is operated on an instruction prefetch basis and provides a 16-bit address output.

The memory module 31 has a capacity f8 of, for example, 256, and 32 units of banks 0 to 7 are formed. Bank 0 is then used as a common area.

This common area contains information 9 similar to the common area C in FIG. 3, such as a bank switching command.

Stores the monitor core and common resources of each bank.

Also, the memory meeting module 32 is the memory module 31
Similarly, it also has the placement of 256.

Banks 8 to 15 of 32K units are formed.

Bank register 6! I is a register in which a selection number for selecting banks 1 to 15 is set, and has a 4-bit configuration in this example.

The decoder 64 decodes the output of the AND φ game and selects the memory module 31 or 32. And (and game) When 0 is output from AO, memory module 31 is selected, and when "1" is output from AND gate AO, memory module 6 is selected.
2 is selected.

AND gates A1 to A6 constitute bank selection gate means, and select any one of banks O to 7 and 8 to 15 of memory module 31j2. 16 outputted from the processor 61
The most significant one of the bit address signals is controlled to be on/off depending on whether it is "1" or zero, and when it is zero, each of the AND gates A1 to A3 selects either bank O or 8, which is zero. At this time, the AND gate AD also outputs zero, and the decoder 64 outputs "1" to the memory module 31 and zero to the memory module 62, thereby selecting the memory module 31. Therefore, when the most significant bit of the 16-bit address output from processor 60 is zero, common area bank 0 is selected, and bank 0 is accessed using the remaining 15 pits. Therefore processor 6
When the most significant bit of the address output of 0 is 0, that is, when the processor address is 0 to 32 or 11, the memory is stored regardless of the contents of the bank register 33.
The area of bank 0 of module 1-31, ie, the common area, is accessed.

When the address is 52 to 64-11, ``0OO1j'' is set in /(link register 6B, and the processor
The most significant bit of the address is "1". As a result, two accesses are performed on the address part of block 1 (specified by the remaining 15 bits).

In this way, in the present invention, bank 0 becomes a common area, and bank 1 and subsequent banks become bank sections that are switched and selected based on the data set in the bank register 33.

Therefore, in the system shown in FIG. 4, the processor 30 sees the memory map 1/c as shown in FIG. Then, when bank register 33K M 001'', that is, 9 is set, the shaded area in FIG.
In other words, banks 0 and 9 appear to be 64 consecutive address spaces.

Now set the processor address to m (m=16 in the example in Figure 4).
), memory module address n (n = 18 in the example in Figure 4) + puncture register 1! (In the example of FIG. 4, e=4), the number of lines to be decoded by the decoder 34 is e-(n-(m-1)), which is 1 in the case of FIG. Gate people 1 to A3 are n-(
m-1) bits. Each bank is accessed using m-1 bits.

However, as can be seen from Figure 4, the BANK register value of the present invention is + all O, and bank 0 is selected even if the processor address is 32 to 64 or 11, so all O is prohibited during operation. It's better.

In the conventional case, there is no such restriction.

〔Effect of the invention〕

According to the present invention, since no unused area is formed in the memory module, the common area can be widened and memory usage efficiency can be greatly improved. Furthermore, since it is only necessary to control the AND gates AO to A3 using the most significant bit of the processor to determine whether or not it is a common area, there is no need to slow down the machine cycle.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the bank system, Fig. 2 is an explanatory diagram of its problems, and Fig. 3 is an explanatory diagram of the conventional instruction preemption puncture system.
FIG. 4 is a configuration diagram of an embodiment of the present invention. FIG. 5 is a memory map. In I, 23 is a bank tube register, 24 is a decoder, 25
60 is an address determination unit, and 60 is a processor. 31.32H memory module, 331'l: bank register, 34 indicates decoder. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani 2 Figure C Ino (B) $5 Figure

Claims (1)

[Scope of Claim] A data processing device having a plurality of banks and a processor constituting a memory, comprising one or more memory modules, a plurality of banks provided in this memory module, and a bank number in which the bank number is held. The apparatus comprises a holding means, a decoder, and a bank selection address/gate means, and when the most significant pit of the processor has a specific value of 1 or zero, the bank selection address/gate means has a zero output. In other cases, a bank is selected according to data held in the bank number holding means.