JPS5917759A - Frequency dividing synchronous detector - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a circuit, by setting frequencies of two reference carrier waves, which are reproduced from an input modulated wave signal, to values which are obtained by dividing the carrier frequency of the modulated wave signal to one-odd numbers. CONSTITUTION:A modulated wave Vs(t) inputted to a terminal 1 is inputted to terminals D of FFs 11 and 12, and terminals Q of FFs 11 and 12 are connected to output terminals o11 and o12. A COSTAS loop for obtaining reference carrier waves is formed by leading Q outputs of FFs 11 and 12 to an exclusive OR circuit 13 and leading the output of the circuit 13 to a multivibrator 15 through a loop filter 14. The output of the multivibrator 15 is led to a 4-frequency dividing circuit constituted with FFs 16 and 17, and the -90 deg. output of this circuit is a terminal T of the FF12 through an inverting circuit 18, and the 0 deg. output is led to the terminal T of the FF11. The oscillation frequency of the multivibrator 15 is set to 4/n (n<= odd number 3) of a carrier frequency fc of the input modulated wave Vs(t). Consequently, a frequency fr of reference carrier waves inputted to terminals T of FFs 11 and 12 becomes fc/n, and orthogonal two-phase modulated wave detection outputs are obtained from terminals o11 and o12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a frequency division synchronous detector suitable for digital integrated circuit implementation.

[Description of prior art]

Conventionally, when performing digital transmission in wireless communications, digital angle modulation methods such as phase shift keying and frequency shift keying are often used.In order to demodulate these digitally modulated waves with a low error rate, ,
It is known that a synchronous detector is effective.

FIG. 1 shows a circuit diagram of such a conventional synchronous detector, particularly a synchronous detector constructed of digital logic elements and suitable for integration into an integrated circuit.

This synchronous detector is a di-wave detector that detects a two-phase phase modulated wave, and is configured to sample and hold the modulated wave using a reference phase carrier wave in order to obtain a detection output. The carrier wave is regenerated with a Costas loop.

In this synchronous detector, the input modulated wave ν5 (11) is applied to the D terminal of the D-type flip-flop 1.2 via the input terminal ■. A reproduction reference carrier wave corresponding to the carrier frequency Oo and 190° of the input modulated wave Vs (tl) is input, and at the rising edge of the input signal to the T terminal, the input modulated wave input to the D terminal It functions to sample Vs(tl, send it to the Q terminal, and hold it until the next rising point. As a result, a binary detection output can be obtained at the detector output terminal 01.

A Costas loop for obtaining a reproduction reference carrier wave leads the Q terminal outputs of the D-type flip-flops 1 and 2 to an exclusive OR circuit 3, and passes the output of this exclusive OR circuit 3 through a loop filter 4. Via Multi Pie Break 5
, and further leads the output of the multi-pie break 5 to the T terminals of the D-type flip-flops 1 and 2 via a 4-frequency divider circuit made up of D-type flip-flops 6 and 7. The loop filter 4 is a manually modulated wave Vs(tl
A DC voltage proportional to the difference between the phase of the carrier wave and the phase of the reproduction reference carrier wave is extracted, and this DC voltage is input to the multi-pie break 5 as a control voltage. The frequency of the multi-pie break 50 oscillation output is the human power modulation wave V
The carrier wave frequency fC of s(tl is four times the frequency fC, that is, 4fc, and this oscillation output is divided by four by the D-type flip-flop 6.7 to become a reproduction reference carrier wave of frequency fC.

The above has described a detector for two-phase modulated waves, but digital FM with a modulation index of 0.5 (MSK: M
ini+++um frequency 5hift
Keying) can also be detected using a similar synchronous detector. However, in this case, it is necessary to add a second exclusive OR circuit 8 as shown in FIG. 2 between the exclusive OR circuit 3 of the Costas loop and the loop filter 4, and this A signal obtained by dividing the frequency of the reproduced clock of frequency fb by two is inputted to one input terminal of the digital OR circuit 8. By forming such a Costas loop, output terminals 01 and 02 obtain the in-phase component and quadrature component of the MSK, i.

In the conventional synchronous detection method explained above, multi-high break 5
It is necessary to set the oscillation frequency to 4rc. As the oscillation frequency of the multi-piebreak 5 increases in this way, the power consumption in the multi-piebreak 5 and the D-type flip-flop 6.7 increases, making it difficult to reduce power consumption.
Another disadvantage is that frequency setting errors increase, making design generally difficult.

[Purpose of the invention]

The present invention solves the above-mentioned drawbacks, and aims to provide a frequency division synchronous detector having a configuration that can reduce the power consumption of the circuit and reduce the frequency setting error of the oscillation circuit during manufacturing. .

[Key points of the invention]

The present invention is characterized in that the frequency of the reference carrier wave reproduced by the carrier wave regeneration circuit is set to an odd number fraction of the carrier wave frequency of the manually modulated wave.

[Explanation based on examples]

Hereinafter, the present invention will be explained based on the drawings.

FIG. 3 shows a circuit diagram of a frequency-divided synchronous detector according to an embodiment of the present invention, and this detector is for detecting a two-phase modulated wave.

In FIG. 3, the input modulated wave Vs (see below) is input to the D terminal of the D-type flip-flop 11.12 via the input terminal ■, and the Q terminal of this D-type flip-flop 11.12 is output to the Connected to .012.

The Costas loop for obtaining the base/$ carrier wave is led to the D-type flip-flops II and 12 (IM child output exclusive OR circuits 13, respectively), and this exclusive OR circuit 1
The output of 3 is led to the multi high break 15 via the loop filter 14, and then the multi high break 15
The output of the D-type flip-flop 16 and 17 is led to a 4-frequency divider circuit, and the 190° output of this 4-frequency divider circuit is connected to the D-type flip-flop 12 through an inverting circuit 18.
The F terminal and the O° output are connected to the D type flip-flop 11.
It is constructed by leading each to the T terminal of

In this Costas loop, the oscillation frequency of the multi-high break 15 is set to 1/3 of the conventional example described above, that is, 4/3 of the general transmission frequency fc of the input modulated wave Vs(t). Ru. Therefore, the frequency rr of the reference carrier wave input to the T terminals of the D-type flip-flops 11 and 12 becomes f r =f c /3 by passing through the frequency divider circuit. As the output of the 4-frequency divider circuit, a reference carrier wave whose phase coincides with Oo and -90° of the carrier frequency of the input modulated wave Vs (tl) is obtained, but the reference carrier wave whose phase is 190° is output from the inverting circuit 18. The signal is converted to a phase of +90° and guided to the D-type flip-flop 12.

Next, the operation of the detector of this embodiment will be explained.

FIG. 4 is a waveform diagram of a reference carrier wave for explaining the operation of the detector of this embodiment.

fa) in FIG. 4 shows the waveform of the reference carrier wave reproduced by the Costas loop of the conventional synchronous detector. This reference carrier wave is shown with phases of 0° and -90°, and its frequency fr is equal to the carrier frequency rc of the received input modulated wave Vs(t).

In addition, (bl indicates the reference carrier wave regenerated by the Costas loop of the frequency-divided synchronous detector according to the present invention, and the phase at 190° with respect to Oo of the output of the frequency divider circuit 18, and the inverter circuit 18 The frequency fr of this reference carrier wave is one-third that of the conventional carrier, that is, f r = f c /3.

The D-type flip-flops 11 and 12 perform sampling operations at the rising edge of the waveform of the base/$carrier input to their T terminals, and obtain in-phase and quadrature detection outputs. fat and fb in Figure 4
Compare the waveforms of l.

First, the rising time of the 0° waveform of (Ill) coincides with the rising time of the 0° waveform of (81. However, since the waveform of (bl is divided by 3, The frequency of rises is 1/3.

Next, at the point when the 90° waveform of fbl rises (
The waveform at one 90° of al is falling, but (L+1 -
When the 90° waveform is made into a +90° waveform via the inverting circuit 18, this +90° waveform has the same rising edge as the 90° waveform of (al).The rising frequency is the same as above. It is 1/3.

In this way, since the waveforms at Oo and +90° of (bl in FIG. Synchronous detection can be performed in the same way.Of course, the frequency of rising edges is 1/3 that of the conventional one, so the detection characteristics will be slightly worse than the conventional one, but the degree of deterioration is sufficiently small. It is something.

FIG. 5 is a characteristic diagram of an example in which the error rate of the detector of the present invention was measured in comparison with a conventional detector, and the characteristic (a)
Characteristic (b) shows the error rate of the conventional synchronous detector, and characteristic (b) shows the error rate of the synchronous detector of the present invention in which the reference carrier is one-third that of the conventional one. As is clear from this figure,
The difference between both characteristics (a) and (b) is slight, and the degree of deterioration is small.

Next, we will explain the case where the frequency r of the reference carrier wave is set to one-fifth of the conventional frequency, that is, f r = f c / 5. In this case as well, the same detection operation as described above can be performed. For, f r =
The reference carrier wave at 190° when f c / 5 is:
Since the rising time coincides with the 190° reference carrier wave when fr=rc, the inverting circuit 1 of the above embodiment
8 is no longer necessary.

In addition, when the frequency of the reference carrier wave is 1/1 of the conventional even number, that is, f r - f c / 2, rr = f
c / 4, f r = f c / 6, etc. For even frequency division waves, the rising point of the -90゛ waveform is fr
Since this does not match the rise of the -90' waveform at =rc, synchronous detection cannot be performed.

Further, in the embodiment shown in FIG. 3, an inverting circuit is used to obtain a reference carrier wave of +9°, but the present invention is not limited to this. For example, as shown in FIG. Equivalent operation can be achieved even if the 190' reference carrier wave is guided to the '' terminal of the rough flip-flop 12 without passing through the inverting circuit 18, and the inverting circuit 19 is connected to the Q terminal instead. Furthermore, the configuration of the base f=carrier regeneration circuit is not limited to that of the embodiment, and the point is that the frequency is one-total of the frequency fC of the input modulated wave, and they are orthogonal to each other. Any circuit configuration may be used as long as it can square the two reference carrier waves.

To summarize the above explanation, the present invention: f r = f c / N However, fr: frequency of reference carrier wave fC: Frequency of carrier wave of input modulated wave N: Odd integer of 3 or more and N=3.7, -=4m-1 (However, m is a positive integer) N=5.9, -=4m+1 (However, m is a positive integer) It is.

(Description of Effects) As explained above, according to the present invention, the oscillation frequency of the carrier wave regeneration circuit, that is, the oscillation frequency of the multi-high break, can be lowered to I/H, and as a result, the oscillation frequency of the carrier wave regeneration circuit, that is, the oscillation frequency of the multi-high break, can be lowered to Power consumption can be reduced. For example, CM
In the case of a detector integrated into an integrated circuit using O3-IC technology, the power consumption can be reduced to 1/H by setting the oscillation frequency to 1/H. Although this increases the code error rate due to the ijL key, the parameters can be selected to such an extent that this does not pose a practical problem. Therefore, the present invention is very effective for devices with small battery capacity, such as mobile communications and small radio devices. Furthermore, since the frequency of the reference carrier wave is low, frequency setting errors and the like in IC manufacturing are reduced, improving precision in frequency setting and improving yield.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional digital two-phase PSK synchronous detector. Fig. 2 is a circuit diagram for converting Fig. 1 into a synchronous detector for MSK. FIG. 3 is a circuit diagram of a detector according to an embodiment of the present invention. FIG. 4 is a waveform diagram of the reproduced reference carrier wave. (a) is a waveform diagram of a conventional example. (bl is a waveform diagram of the embodiment of the present invention. Figure 5 is a diagram showing the entertainment rate characteristics in the case of 3 frequency division synchronization. 11.12.16.17...D-type flip-flop 13...exclusive OR circuit 14...Loop filter I5...Multi-vibrator 18.19...
・Inverting circuit patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Takaman Ide 4 Figure 5 °P 3 ° ° ゝ Figure 6

Claims (1)

[Claims] (1) A carrier regeneration circuit that regenerates the M transmission wave (two standards orthogonal to each other) from the input modulated wave signal, and samples the modulated wave signal at the timing according to the two reference carrier waves. In the synchronous detector equipped with a phase detection circuit that obtains in-phase and quadrature detection outputs, the frequency of the two reference carrier waves regenerated by the carrier regeneration circuit is 1/N of the carrier frequency of the modulated wave signal.
(However, the value of N is an odd integer of 3 or more). +21 In the 11Q transmission regeneration circuit, the value of N is 4m-1 (
m is a positive integer), and the phases of the two reference carrier waves are configured to correspond to 0° and +90° of the carrier frequency of the modulated wave signal, respectively. (3) The carrier regeneration circuit has a frequency-divided wave synchronous detector as described in Section 2.
<m is a positive integer), and the phases of the two reference carrier waves are configured to coincide with O゛ and 190° of the carrier frequency of the modulated wave signal, respectively. The frequency-divided synchronous detector described in (1).