JPS59176927A - Driving circuit of switch element - Google Patents

Driving circuit of switch element

Info

Publication number
JPS59176927A
JPS59176927A JP58051331A JP5133183A JPS59176927A JP S59176927 A JPS59176927 A JP S59176927A JP 58051331 A JP58051331 A JP 58051331A JP 5133183 A JP5133183 A JP 5133183A JP S59176927 A JPS59176927 A JP S59176927A
Authority
JP
Japan
Prior art keywords
resistance
switching
diode
gate
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58051331A
Other languages
Japanese (ja)
Other versions
JPH0363850B2 (en
Inventor
Satoru Ishii
哲 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP58051331A priority Critical patent/JPS59176927A/en
Publication of JPS59176927A publication Critical patent/JPS59176927A/en
Publication of JPH0363850B2 publication Critical patent/JPH0363850B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0013Arrangements for reducing power consumption in field effect transistor circuits

Abstract

PURPOSE:To minimize power loss with a switching element by using a serial circuit consisting of a diode and a resistance and an inductive element which are set in parallel to said diode to form a driving circuit of a semiconductor element for switching operation. CONSTITUTION:The gate driving circuits of switching semiconductor elements Q1 and Q2 consist of a serial circuit containing diodes D1 and D2 connected in the direction where the conduction is prevented for the elements Q1 and Q2 respectively and a resistance R1 and an inductive IND element L1 which are parallel to the diodes D1 and D2 as well as a serial circuit of a resistance R2 and an IND element L2. When a step type signal is impressed in forward direction to an input terminald 1, the gate voltage of the element Q1 shows the synthesization of a curve which rises up with a time constant obtained by the inter- electrode capacity between the R1 and the Q1 and a curve produced by the L1 and the inter-electrode capacity. This gives some delay to the time during which the Q1 is turned on and prevents that both Q1 and Q2 are simultaneously turned on. Furthermore the gate bias is deepened after the Q1 is turned on, and therefore the ON resistance is reduced. This attains a switching operation with small power loss.

Description

【発明の詳細な説明】 不発明はスイッチ素子の、駆動回路に関し、特にスイッ
チングIIW作時に4曲する時のスピードをやや遅くシ
、非導通になる時のスピードを速くするようにし、素子
における電力損失を極小に抑えるようにした駆動回路に
関する。
[Detailed Description of the Invention] The present invention relates to a drive circuit for a switching element, and in particular, the speed at which the switch turns 4 during switching IIW is made slightly slower, and the speed at which it becomes non-conducting is increased, thereby reducing the power consumption in the element. The present invention relates to a drive circuit that minimizes loss.

従来、こOJ棟の回路としては第1図に示すものがあっ
た。図において、1は入力端子であり、ダイオードL1
.のカンードおよび抵抗R1の一端がk iEされてい
る。タイオードD、のアノードおよび抵抗R,の曲端は
NチャネルF E T Q、のゲートに@続さtしてい
る。このF E 1’ Qtのドレインは出力端子2に
導かれ、ソースは負電源3に接続される。また、これと
は逆極性の構成がダイオードD? 抵抗R,,Pチャネ
ルF E T Qtによりなされ、入力端子4が設けら
れ正電源5が供給されている。
Conventionally, the OJ building's circuit was as shown in Figure 1. In the figure, 1 is the input terminal, and the diode L1
.. and one end of the resistor R1 are k iE. The anode of the diode D, and the curved end of the resistor R, are connected to the gate of the N-channel FET Q. The drain of this F E 1' Qt is led to the output terminal 2 , and the source is connected to the negative power supply 3 . Also, the configuration with the opposite polarity is diode D? It is made up of resistors R, , P-channel FET Qt, is provided with an input terminal 4, and is supplied with a positive power source 5.

なお、FETQrには図に示すように、ゲートドレイン
間、ゲートソース間に電極間容量CI。
Note that, as shown in the figure, FETQr has interelectrode capacitance CI between the gate and drain and between the gate and source.

C7が各々存在している。一方、PチャネルFETQ2
にも同様に電極間容量が存在する(図示せず)。
C7 is present in each case. On the other hand, P channel FETQ2
Similarly, there is an interelectrode capacitance (not shown).

次に動作について説明する。入力端子1および4には直
流レベルの異なる同位相の方形波が供給されるが、FE
TQr側について見ると、オン・オフ時には、電極問答
JftCx、 C2を充放電する必要がある。ゲートか
ら入力側を見ると、オン時は抵抗R1v オフ時はダイ
オードD、の順力量J1(杭がそiシそれ信号掠インピ
ータンスになるため、芥財CI+  Ctを充放電する
スピードは、オン時に遅く、オフ時に速くなる。この入
力端子1及びF E T Qlのゲートの重圧波形を第
2図(alにボす。また、F E T Qt 111!
Iも同様な動作をするため、F E T Ql −Qt
が同時に導通することを防止することができる。
Next, the operation will be explained. Input terminals 1 and 4 are supplied with in-phase square waves with different DC levels, but the FE
Looking at the TQr side, it is necessary to charge and discharge the electrodes JftCx and C2 when turning on and off. Looking at the input side from the gate, the resistance R1v is on when it is on, and the diode D is on when it is off. When it is off, it is slow, and when it is off, it becomes fast.The pressure waveform of this input terminal 1 and the gate of FET Ql is shown in Figure 2 (al).
Since I also operates in the same way, F E T Ql −Qt
can be prevented from becoming conductive at the same time.

ところで、一般にFETけゲートバイアスを深く印加し
た方が、オン抵抗が小さくなるので、この場合のオン4
1(抗の変化は第2図(blのようになる。
By the way, in general, the deeper the gate bias is applied to the FET, the smaller the on-resistance becomes.
1 (The change in resistance is as shown in Figure 2 (bl).

すなわち、オンii¥後はオン抵抗が比較的大きく、ゲ
ートバイアスが深くなるにつれて徐々に小さくなる。こ
のため、スイッチ動作ζせているにもかかわらず、FE
Tにおける電力損失が比較的大^く々ってしまうという
欠点があった。
That is, the on-resistance is relatively large after turning on, and gradually decreases as the gate bias becomes deeper. For this reason, despite the switch operation ζ, the FE
The disadvantage is that the power loss at T is relatively large.

木兄りI 1.f 、上り己のよう々従来のものの欠点
を除去するために成をれたもので、ゲート駆動回路の一
部にインタクチイブ素子を用いることにより、一対のス
イッチ素子が同時に導通するこ七を防ぐとともに、スイ
ッチ素子における電力損失を極小に抑えることができる
スイッチ素子の駆動回路を提供することを目的としてい
る。
Tree Brother I 1. f. This was developed in order to eliminate the drawbacks of conventional ones such as the above one, and by using an inactive element in a part of the gate drive circuit, it is possible to prevent a pair of switching elements from becoming conductive at the same time. An object of the present invention is to provide a drive circuit for a switch element that can minimize power loss in the switch element.

以下、本発明に関し、図に基いて説明する。Hereinafter, the present invention will be explained based on the drawings.

第3図は本発明の一実施例を示す回路図であり、第1図
の回路との変更点は抵抗R1およびR1に直列にインタ
クチイブ素子りおよびり、をそれぞれ挿入した点である
FIG. 3 is a circuit diagram showing an embodiment of the present invention, and the difference from the circuit of FIG. 1 is that resistors R1 and RI and R1 are inserted in series with resistors R1 and R1, respectively.

このインタクチイブ素子L+、  R2は小さなインダ
クタンスを有し、コイルやビーズコアにより構成きれる
。また、抵抗R,,R,の値は第1図の場合より小きく
設定する。
The inactive elements L+ and R2 have small inductance and can be constructed from coils or bead cores. Further, the values of the resistors R, , R, are set smaller than in the case of FIG.

次に本発明の動作について説明する。Next, the operation of the present invention will be explained.

F E T Q、がオンからオフへ移行する場合は従来
と同様であるが、オフからオンへ移行するときのゲート
波形が大幅に異なる。入力端子lに正方向へステップ状
の信号が印加されると、ゲート電圧は、抵抗R,と電極
間容量(ミラー効果分も言む)とによる時定数で上昇す
る曲線と、Llと電極間容量とで生じる共振(抵抗1尤
、でダンプきれているため減材振動となる)曲線との合
成となり、第4図(alに示すような波形となる。
The transition from ON to OFF is the same as in the conventional case, but the gate waveform when transitioning from OFF to ON is significantly different. When a step-like signal is applied to the input terminal l in the positive direction, the gate voltage rises with a time constant due to the resistance R and the capacitance between the electrodes (also referred to as the Miller effect), and the curve between Ll and the electrode. This is a combination of the resonance curve caused by the capacitance (resistance is damped by 1 force, resulting in material reduction vibration), and a waveform as shown in FIG. 4 (al) is obtained.

これによつ? 、F I: T CJ+がオンになるま
での時間を若干遅らせることができ、F’ETQ+、Q
tが同時にオンすることを防ぐことができるという従来
回路の4u点を残しつつ、しかもオン後単時間でゲート
バイアスが深くなって、第4図(b)に示すようにオン
直後からオン抵抗を小さく抑えることができる。したが
って、1(イカ損失の不妊いスイッチング動作が可能と
なる。
What about this? , F I: T The time until CJ+ turns on can be slightly delayed, and F'ETQ+, Q
While retaining the 4u point of the conventional circuit that can prevent t from turning on at the same time, the gate bias becomes deep within a short period of time after turning on, and the on-resistance increases immediately after turning on, as shown in Figure 4 (b). It can be kept small. Therefore, a switching operation with no loss of 1 (squid) is possible.

従って、上記実施例ではD級増幅器の出力段にそのまま
用いることができる。
Therefore, the above embodiment can be used as is in the output stage of a class D amplifier.

また、上記の例ではソースがコモンになっている例を示
したが、第5図に示すようにドレインがコモンになって
いる回路でも同様の効果を奏する。また、46図に示す
ように、同極性(Pチャネル)FETQl、(hのトレ
インとソースとおしを接続して出力端子2とし、FET
QIのソースを負電源3に、Ei’E’1’Q2のドレ
インを正ttj、’ iJ:F、 5に夫々接続するよ
うな構成であってもよい。
Further, although the above example shows an example in which the source is common, a circuit in which the drain is common, as shown in FIG. 5, can produce the same effect. In addition, as shown in Fig. 46, the train and source of the same polarity (P channel) FET Ql, (h are connected to output terminal 2, and the FET
The configuration may be such that the source of QI is connected to the negative power supply 3, and the drain of Ei'E'1'Q2 is connected to the positive ttj,'iJ:F,5, respectively.

さらに、スイッチング電源に用いる例を第7図に示す。Furthermore, an example of use in a switching power supply is shown in FIG.

サブトランス1゛1によって、FETQ。FETQ by sub-transformer 1-1.

およびQtが交互にオンするようになされており、メイ
ントランスT、によって負荷6を駆動する。
and Qt are turned on alternately, and the load 6 is driven by the main transformer T.

この例でもF E T Ql 、Qtが同時にオンする
ことを埒けるために上述の駆動回路を用いている。
In this example as well, the above-mentioned drive circuit is used to prevent F E T Ql and Qt from being turned on at the same time.

この例ではプッシュブルカ式の電源を示したが、他の方
式でも同様な考え方を用いることができる。
Although this example shows a push burqa type power supply, the same concept can be used with other systems as well.

また、上記の例でけFETを用いた場合について説明し
たが、トランジスタであってよく、電極間容量を利用し
ていれば、本発明の範囲に含まれる。
Further, although the above example describes the case where a FET is used, a transistor may be used, and as long as inter-electrode capacitance is utilized, it is within the scope of the present invention.

以上のように、本発明によれは、駆動回路に用いたイン
タクチイブ素子と、スイッチング素子の電極問答敬との
共振による減衰撮動を利用するように構成したので、オ
ン直後からオン抵抗を小さくすることができ、しかも、
一対のスイッチング素子を同時にオンはせることがない
ため、効率の良いスイッチング回路を実現することがで
きる。
As described above, the present invention is configured to utilize attenuation imaging due to resonance between the interactive element used in the drive circuit and the electrode contact of the switching element, so that the on-resistance is reduced immediately after turning on. can be done, and
Since a pair of switching elements are not turned on at the same time, an efficient switching circuit can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のスイッチング回路を示す回路図、第2図
は従来の回路の動作を説明するだめの波形例を示す図、
第3図は本発明の一実施例を示す回路図、第4図は本発
明の詳細な説明するための波形例を示す図、第5. 6
. 7図は本発明の他の実施例を示す回路図である。 Qs、Qt・・・・・・FET R,、R,・・・・・・抵抗 り、% D、・・・・・・ダイオード Ll、  L2・・・・・・インダクテイプ素子特許出
願人  パイオニア株式会社 第2図 第7図
FIG. 1 is a circuit diagram showing a conventional switching circuit, and FIG. 2 is a diagram showing an example of waveforms to explain the operation of the conventional circuit.
FIG. 3 is a circuit diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing waveform examples for explaining the present invention in detail, and FIG. 6
.. FIG. 7 is a circuit diagram showing another embodiment of the present invention. Qs, Qt...FET R,, R,...Resistance, % D,...Diode Ll, L2...Induct tape element patent applicant Pioneer Corporation Company Figure 2 Figure 7

Claims (1)

【特許請求の範囲】[Claims] スイッチング動作用半導体素子と、前記半導体素子の4
荊・非導通を制御するだめの信号を印加する入力端子と
、前記半導体素子と入力端子間に前記半導体素子の導通
を阻止する方向に接続きれたダイオードと、前記タイオ
ードと並列に接続された抵抗とインダクテイプ素子の1
tI列回路とを備えたことを特徴とするスイッチ素子の
駆動回路。
a semiconductor element for switching operation; and 4 of the semiconductor elements.
An input terminal for applying a signal for controlling non-conduction, a diode connected between the semiconductor element and the input terminal in a direction to prevent conduction of the semiconductor element, and a resistor connected in parallel with the diode. and induct tape element 1
1. A switch element drive circuit comprising: a tI column circuit.
JP58051331A 1983-03-26 1983-03-26 Driving circuit of switch element Granted JPS59176927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051331A JPS59176927A (en) 1983-03-26 1983-03-26 Driving circuit of switch element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051331A JPS59176927A (en) 1983-03-26 1983-03-26 Driving circuit of switch element

Publications (2)

Publication Number Publication Date
JPS59176927A true JPS59176927A (en) 1984-10-06
JPH0363850B2 JPH0363850B2 (en) 1991-10-02

Family

ID=12883934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051331A Granted JPS59176927A (en) 1983-03-26 1983-03-26 Driving circuit of switch element

Country Status (1)

Country Link
JP (1) JPS59176927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009055521A (en) * 2007-08-29 2009-03-12 Mitsubishi Electric Corp Semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009055521A (en) * 2007-08-29 2009-03-12 Mitsubishi Electric Corp Semiconductor apparatus

Also Published As

Publication number Publication date
JPH0363850B2 (en) 1991-10-02

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